Impact of O2 post oxidation annealing on the reliability of SiC/SiO2 MOS capacitors*

Peng Liu(劉鵬) Ji-Long Hao(郝繼龍) Sheng-Kai Wang(王盛凱) Nan-Nan You(尤楠楠)Qin-Yu Hu(胡欽宇) Qian Zhang(張倩) Yun Bai(白云) and Xin-Yu Liu(劉新宇)

1Key Laboratory of Microelectronics Devices&Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China

2University of Chinese Academy of Sciences,Beijing 100049,China

3High-Frequency High-Voltage Device and Integrated Circuits R&D Center,Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China

Keywords: SiC,O2 post oxidation annealing,interface traps,MOS

1. Introduction

Silicon carbide (SiC) is a promising material for power electronics because of its wide band gap and high thermal conductivity. Additionally, SiC is able to grow SiO2by thermal oxidation,a conventional way similar to silicon,which is one of the unique advantages of SiC over the other compound semiconductors.[1]At present, most of the world’s leading semiconductor device manufacturers have made great progress in the production of SiC MOSFET devices. But for the oxidation treatment of SiC materials, too high or too low oxidation temperature leads to the existence of oxygen vacancy and residual carbon in gate oxide materials.

To reduce interface defects on SiC, although many progresses have been reported by using novel treatment methods, such plasma oxidation and ALD growth of high-kdielectrics,[2-6]thermal oxides with proper POA treatments,such as H2, NO, N2O, H2O, N-O mixed plasma, H-Cl-N(10% HCl-N2) mixed plasma, and so on, are still the main stream for dielectric growth on SiC because of their relatively high reliability.[7-14]Among the above various annealing ambient,O2is the most fundamental case to study carbon-related behaviors during POA treatment, because of no introduction of additional elements. Previously, it has been found that the gas flux,which is defined by the product of annealing time and pressure, is the main factor that affects the interface state for O2POA.In specific,an optimized process window at low pressure region(～0.1 bar,1 bar=105Pa)is proposed to improve the interface quality of SiC MOS with applicable annealing duration(not too long or too short time span).[15]However,as another important factor except annealing time and pressure,the influence of temperature on the reliability of SiC/SiO2stacks needs further study. Furthermore, for O2POA, although there are several pioneering instructive works.[16-23]From the viewpoint of reliability, besidesDit, TDDB characteristics,gate-leakage density,breakdown field and their relationship still need to be further investigated.

In this work, we study the effect of dry O2annealing at different temperatures on theDitof SiC/SiO2stacks,and further explore the effect ofDitof SiC/SiO2MOS stacks on the electrical properties of the oxide,such asJgand TDDB characteristics. Moreover, the area dependence of TDDB characteristics for thermal gate oxide on SiC is studied.

2. Experiment

After standard RCA cleaning, SiO2was grown by dry O2oxidation of n-type 4H-SiC epitaxial layer at 1300°C for 30 minutes followed by cooling down in N2gas with a rate of 10°C/min. Note that before cooling down process,oxygen was pumped out from the chamber to less than 1 Pa within 10 seconds.Therefore,the as-oxidized sample can be regarded as the one without any POA treatments. The thickness was confirmed to be 50 nm by 1 MHzC-Vmeasurement. The epitaxial layers were grown on (0001) Si face 4H-SiC substrate with a thickness of 12 μm,a 4°-off angle and an effective carrier density(Nd-Na)of about 7.81×1015cm-3. POA treatments were carried out at 0.1-bar dry oxygen ambient for 5 minutes with a temperature range of 800°C to 1000°C,respectively. The details are listed in Table 1. After the thermal oxidation and POA treatments, 500-nm-thick aluminum top electrodes with areas of 0.68×10-2mm2,1.83×10-2mm2,and 3.58×10-2mm2(confirmed by optical microscope)were formed by thermal evaporation with metal mask. Then, after polishing the SiC substrate backside with a diamond-pen,aluminum with thickness of 500 nm was directly evaporated to achieve back ohmic contact. Keysight B1500A and E4990 LCR meters were used forI-VandC-Vcharacterizations.

Table 1. Detailed POA conditions for SiC/SiO2 stacks.

3. Results and discussion

Figure 1 shows the typical time-zero dielectric breakdown(TZDB) breakdown behavior of as-oxidized SiO2/SiC stacks(step = 0.1 MV·cm-1·s-1), which consists of soft breakdown and hard breakdown.[24]A large current jump corresponds to a hard breakdown event.[25]In general,gateJgwith a sudden jump exceeding 3 orders can be regarded as hard breakdown.[26]The soft breakdown part is the area where theJgincreases obviously without hard breakdown,and the electric field of gate oxide (Eox) from 6 MV/cm to the intrinsic breakdown field(Eint)is the soft breakdown part.

Fig. 1. Typical breakdown behavior of as-oxidized sample of thermal gate oxide on SiC.When Jg jumps suddenly, the value of the corresponding Eox is the Eint. The Eint can guide us to determine the range of Estr,usually 90%of the Eint is taken as the Estr.

The gate oxide is tested by TDDB with constant stress electric feild (Estr) which is determined by TZDB test. The statistics of gate oxide TDDB tests are usually described by the Weibull distribution[27]

whereβis called the slope parameter. This Weibull slopeβis an important parameter to determine the homogeneity level when evaluating gate-oxide reliability.βhas a useful property such that if the area is increased by a factor(A1/A2),then the distribution is shifted by a factor of ln(A1/A2),and the characteristic lifetimeα1would be decreased toα2according to the following expression:[28]

Figure 2(a) shows time-to-breakdown (Tbd) distributions obtained from TDDB test of SiC MOS capacitors with three electrode areas. For each area, the plots can be divided into two regions: the initial failure region and the random failure region according to the bathtub curve analysis.[29]Figure 2(b)just shows the data related to random failure, where the data with failure rate ofF ＜63.2% are attributed to initial failure and therefore can be eliminated.

Fig. 2. TDDB Weibull distribution of as-oxidized sample of thermal gate oxide on SiC with fxiing Estr=8.55 MV/cm and varying electrode area. (a)Initial failure and random failure;(b)just random failure.

With the decrease of electrode area from 3.58×10-2mm2to 0.68×10-2mm2, the corresponding Weibull slopes are 1.53, 1.40, and 1.55, respectively. Within the error range of 10%,the three Weibull curves are nearly parallel.The ratio between initial failure samples and total samples inTbdare 24/37, 23/36, and 17/30 respectively, which are obtained according to the number of the same electrode areaTbdin Figs. 2(b) and 2(a). The larger the area of MOS capacitor gate,the larger the proportion of initial failure inTbddistributions. Hatakeyamaet al.suggested that the surface defects are one of the major causes of initial failure.[30]With the change of the electrode area,the Weibull slopeβdoes not change,but the characteristic lifetimeαchanges. In specific, the smaller the electrode area,the larger the characteristic lifetimeα.

Figures 3(a)-3(d) areJg-Eoxdiagrams of as-oxidized,dry-800, dry-900, and dry-1000 samples respectively. For each figure,the data are plotted from 5 samples with the same condition. Obviously, from initial to soft breakdown, five curves are nearly overlapped,suggesting the good uniformity of the sample, making it possible for the following comparison onJgandEint.As depicted in Figs.3(a)-3(d),theEintfrom small to large is dry-800,as-oxidized,dry-1000 and dry-900.

Fig.3. (a)-(d)Jg-Eox curves of TZDB of MOS capacitor of samples as-oxidized and samples re-oxidized at different temperatures. (e)Direct comparison of the typical TZDB curves of the four groups of samples: as-oxidized, dry-800, dry-900, dry-1000. The inset shows the comparison of leakage current density in soft breakdown region of the four groups of samples.

Figure 3(e) shows the soft breakdown regionJgof four groups of samples atEoxof 6 MV/cm. The inset shows that theJgmeets the following trend,Jg(dry-800)＜Jg(dry-900)＜Jg(dry-1000)＜Jg(as-oxidized). Compared with theJgfrom as-oxidized sample,the ones annealed at 800°C,900°C,and 1000°C show relatively lowerJg, indicating that POA treatment is beneficial for enhancing the dielectric quality and suppressing the gate leakage. When elevating the POA temperature from 800°C to 1000°C,Jgis found to increase,suggesting that the quality is sensitive to POA temperature.

For Fig.3(b),it is noted that a common phenomenon with“step-like”current jump near the hard breakdown field exists when compared with those in Figs. 3(a), 3(c), and 3(d), suggesting that a bilayer continuous breakdown might occur for 800-°C POA sample. In order to further investigate the effect during POA at 800°C, it is necessary to study the interface characteristic by consideringDit. This will be discussed in next section.

Fig.4.(a)Dit of SiC MOS capacitors at different POA temperatures with 0.1-bar pressure for 5 minutes as a function of the surface potential. (b)TDDB Weibull distributions (only random failure) of thermal gate oxide on SiC at different POA temperatures with a fixed electrode area.

Figure 4(a) shows theDitprofiles extracted by conductance method from SiC/SiO2MOS capacitors with different POA conditions. As shown in Fig. 4(a), at the energy level of 0.2 eV below the conduction band edge of SiC,Dit(dry-800)＜Dit(dry-900)＜Dit(dry-1000)＜Dit(As-oxidized).Compared with theDitfrom as-oxidized sample,the ones annealed at 800°C,900°C,and 1000°C show relatively lowerDit,indicating that POA treatment is beneficial for eliminating interface states in the temperature range of 800°C to 1000°C.However,with the increase of POA temperature,the reduction ofDitis decreasing. The above-mentioned trade-off behavior seems to be related to the phenomenon in Fig.3(e).

Figure 4(b)shows the TDDB Weibull distribution of thermal gate oxide on SiC at different POA temperatures with a fixed electrode area of 1.83×10-2mm2. TDDB is limited only by the quality of the oxide and the interface, and not by the intrinsic properties of the SiC.[31]So the two different Weibull slopesβwhich are extracted by linear fitting the two regions in Fig.4(b)represent the breakdown characteristics of the transition layer and SiO2layer respectively. Concerning the reason for the two slopes, it can be explained by considering the distribution of residual carbon across the interfacial transition layer and the SiO2film. Compared with SiO2, the interfacial SiOxCytransition layer is a carbon-rich one,therefore the breakdown field of the interfacial transition layer should be lower, because residual carbon is the major origin of interface traps.[32,33]

Moreover, from the aspect of POA temperature dependence, as shown in Fig. 4(b), the sample annealed at 800°C shows the longestTbdwhen compared with the as-oxidized one and the ones annealed at higher temperature. According to Figs.3(e),4(a),and 4(b),similar trade-off distributions against POA temperature are demonstrated,suggesting thatJg,Dit, andTbdare strongly correlated. Therefore, starting from the consistency in Figs.3(e),4(a),and 4(b),the data are summarized and re-plotted in Fig.5(a)for comparison.Figure 5(a)shows theJg,the inverse median lifetime of TDDB(1000/τ)and theDitvalues atEc-0.2 eV with different POA conditions. Note the median lifetimeτof TDDB is obtained from Fig.4(b)atF=63.2%,and the inverse value ofτis used here for direct comparison because all the three parameters are required to be low for gate stack quality improvement. Compared with the other three conditions, the POA treatment at 800°C is obviously the lowest in the above three key indicators. In order to explain the three trade-offs in Fig. 5(a), a plausible model is proposed in Fig. 5(b) by considering two competing reactions and a critical temperatureTcas follows.

For the two competing reactions,one is related to the reaction with interstitial carbon atom and oxygen vacancy, and the other one is related to the reaction with C-Si bond,both of them are oxidation reactions,this is consistent with the previous research by Zhuet al.and Kitaet al.[22,34]

On the one hand,the increase of POA temperature is beneficial to removing the residual carbon in the transition layer and reducing the density of interface states.During POA treatment, as reported by Wang group,[22,23]carbon releases from SiOxCyin the form of CO or CO2and the SiOxCytransformation into higher oxidation states,thus reducing the SiOxCycontent and the interface transition region thickness. On the other hand, it enhances the reaction between oxygen atoms and SiC,and increases the density of interface states. This is consistent with the model proposed by Song et al. and the experimental results by Gotoet al.[35,36]SiC/SiO2becomes less stable at high temperature,and tends to form oxygen vacancies and residual carbon.[37]

Fig. 5. (a) The Jg, the inverse median lifetime of TDDB (1000/τ), and the Dit values at 0.2 eV energy level below the edge of SiC conduction band for sample as-oxidized,dry-800,dry-900,and dry-1000. (b)Two competing reactions: generation of residual carbon and elimination of residual carbon.

Two competing effects occur simultaneously during annealing,the removal of carbon from the interfacial region and the oxidation of SiC to produce more carbon clusters.[38]According to the SiC oxidation model by Goto and Hijikata,carbon and silicon atoms are emitted from the interface into the oxide layer during thermal oxidation.[39]And the emitted carbon atoms become interstitial carbon in SiO2. Since the interaction between interstitial carbon and surrounding SiO2network is much weaker than the strong covalent C-Si bond,the activation energy of interstitial carbon reaction with oxygen is lower than that of bonded carbon reaction with oxygen. Note that 800°C is sufficiently low temperature to neglect the additional growth of oxide,which does not contribute to the interface deterioration by the low-temperature oxidation.[34]

For MOS capacitor, theDit,Jg, and 1/τ, are all related to the amount of defects in the oxide and at the interface. In this work, we can roughly use the difference of reaction rate between the above mentioned two reactions to evaluate the amount of defects in SiO2and SiO2/SiC interfaces. For both reactions, the reaction rate (R) can be approximately written in the following expression,R=F×exp(-Ea/kBT), whereFis a pre-factor that depends on the reactant concentration,Eais the reaction activation energy,Tis the temperature,andkBis the Boltzmann constant. For the reaction that repairs the SiO2network and SiO2/SiC interface,Fis mainly determined by the interstitial carbon and oxygen vacancy concentration.While for the latter one, it is related to the atomic density of SiC.Compared with the former one,since both interstitial carbon and oxygen vacancy are defects in the thermal oxide,the atomic density of SiC should be significantly larger. In order to make the discussion clearer and easier,we assume that in a short period of time,Fof each reaction is a fixed value. And for comparison of activation energies,as mentioned above,Eaof reaction corresponding to network repairment should be much lower than the one corresponding to oxide growth at the interface during POA. Since the temperature is involved as exp(-Ea/kBT)in the rate expression,as the POA temperature increases,rate grows faster for the reaction corresponding to higherEa.Therefore,as the POA temperature increases,the rate difference between network repairment and oxide growth becomes smaller,and thus results in less improvement of gate stack quality includingDit,Jg, and 1/τin higher POA temperature region. In this work,although only 800°C-1000°C has been investigated,we infer that such trend can be slightly extended to higher temperature(～1100°C or more),because the reaction mechanism does not change. While for the case of POA at＜800°C,although the oxide growth that degrades the interface nearly stops, the POA effect on gate stack improvement also becomes quite limited in short time span such as 5 min in this study, which is consistent with the results by Yinet al. and Kitaet al.[33,34]

Therefore, by considering the above-mentioned tradeoffs, we believe a critical temperatureTcshould exist. For the POA temperature lower thanTc,the removal rate of residual carbon increases with the increase of temperature, while for the POA temperature higher thanTc,it decreases with the increase of temperature, even with a net increase of residual carbon.

In the POA treatment,some residual carbon can be eliminated by oxidizing and repairing the interface,which helps to reduce theDit.And when the temperature is higher thanTc,the rate of residual carbon produced by oxidation increases more with the increase of temperature. At this time,the net elimination rate of carbon residue decreases, leading to the decrease of improvement effect, and finally leading to degradation ofDit, reliability and gate leakage. This trend further confirms the inference about the existence ofTc.

Concerning the step-like jump in TZDB tests of 800-°C POA samples,since 800°C is close toTcbased on our model,thus it is reasonable to believe that the uniformity and breakdown electric field of the interfacial layer at this condition is relatively higher, which makes the TZDB curves different from the other three ones, and causes the segmental breakdown of the two layers.

4. Conclusion

The effect of the O2POA temperature on the gate oxide quality is studied,in terms of gate leakage current density,interface trap density, and TDDB reliability, where trade-off distributions with the same optimized temperature(～800°C)have been demonstrated. A plausible model is proposed by considering two competing reactions,e.g.,the removal of carbon from the interfacial region and the oxidation of SiC to produce more residual carbon, and a critical temperatureTc,which can well explain all the results in this work and strongly indicating that O2POA treatment nearTcis effective in improving the oxide quality on SiC for high performance and reliability devices.