High-PSRR High-Order Curvature-Compensated CMOS Bandgap Voltage Reference

，Yunsong Li，Jinzhao Lin，，Yu Pangand Wei Luo

（1．Chongqing Key Laboratory of Photoelectronic Information Sensing and Transmitting Technology，Chongqing University of Posts and Telecommunications，Chongqing 400065，China；2．College of Computer Science and Technology，Chongqing University of Posts and Telecommunications，Chongqing 400065，China；3．School of Electronic Information and Automation，Sichuan University of Science and Engineering，Zigong Sichuan 643000，China）

High-PSRR High-Order Curvature-Compensated CMOS Bandgap Voltage Reference

Qianneng Zhou1?，Yunsong Li1，Jinzhao Lin1，Hongjuan Li2，Yu Pang1and Wei Luo3

（1．Chongqing Key Laboratory of Photoelectronic Information Sensing and Transmitting Technology，Chongqing University of Posts and Telecommunications，Chongqing 400065，China；2．College of Computer Science and Technology，Chongqing University of Posts and Telecommunications，Chongqing 400065，China；3．School of Electronic Information and Automation，Sichuan University of Science and Engineering，Zigong Sichuan 643000，China）

A high-PSRR high-order curvature-compensated CMOS bandgap voltage reference（BGR），which has the performances of high power supply rejection ratio（PSRR）and low temperature coefficient，is designed in SMIC 0.18 μm CMOS process.Compared to the conventional curvature-compensated BGR which adopted a piecewise-linear current，the temperature characterize of the proposed BGR is effectively improved by adopting two kinds of current including a piecewise-linear current and a current proportional 1.5 party to the absolute temperatureT．By adopting a low dropout（LDO）regulator whose output voltage is the operating supply voltage of the proposed BGR core circuit instead of power supply voltageVDD，the proposed BGR with LDO regulator achieves a well PSRR performance than the BGR without LDO regulator.Simulation results show that the proposed BGR with LDO regulator achieves a temperature coefficient of 2.1×10-6／℃with a 1.8 V power supply voltage and a line regulation of 4.9 μV／V at 27℃.The proposed BGR with LDO regulator at 10 Hz，100 Hz，1 kHz，10 kHz and 100 kHz have the PSRR of-106.388，-106.388，-106.38，-105.93 and -88.67 dB respectively.

bandgap voltage reference；low dropout regulator；temperature coefficient；power supply rejection ratio

1 Introduction

Voltage reference is a fundamental building block in many analogue and mixed signal electronic systems［1-3］，such as data converter，phase lock loop，power management，and so on.The demand for voltage reference should be independent of temperature，power supply and process.In fact，bandgap voltage reference（BGR）is one of the most popular voltage references in analogue and mixed-signal integrated circuits. Conventional BGR，which is inspired by Widlar［4］and Brokaw［5］，is first-order temperature compensation.The basic idea of BGR is a weighted sum of the base-emitter voltageVBEof NPN bipolar transistor and the thermal voltageVT．Due to the nonlinearity ofVBE，first-order BGR has relatively high temperature coefficient（TC）in the whole temperature range，and it is not suited for the requirements of high precision circuits.However，the demand for high-accuracy low-TC BGR is increasing in many industries such as medical electronics，consumer electronics，portable instruments，and so on.

To achieve high-accuracy low-TC BGR，many temperature compensation techniques have been developed［6-15］，such as temperature-dependent resistor ratio technique，resistor-less technique，exponential curvature compensation technique，piecewise compensation technique，and so on.These reported techniques focuse on cancelling the nonlinear dependence of base-emitter voltage to some degree，but their outputs have a relative low power supply rejection ratio（PSRR）in the low frequency.Regarding modern SoC design，there is a growing trend of designing BGR with a high PSRR performance even at high frequency range to reject noise from high speed digital circuits.In the recent past，many approaches have been developed to improve the PSRR of BGR［16-27］.Those reported BGRs with improvement PSRR technique have achieved well PSRR performance，but they have a relatively high TC.So，the high PSRR and low-TC BGR should be still analyzed and designed for the requirements of high precision circuits.

This paper proposes a high-PSRR high-order curvature-compensated CMOS BGR by employing a LDO regulator，a piecewise-linear current and a current proportional 1.5 party to the absolute temperatureT．By adopting two kinds of current which are a piecewise-linear current and a current proportional 1.5 party to the absolute temperatureT，the proposed BGR achieves a well temperature performance than the conventional curvaturecompensated BGR which adopted only a piecewiselinear current.The proposed BGR achieves a well PSRR performance in a wide frequency range by adopting the technique of LDO regulator than the designed BGR without LDO regulator.And then the proposed high-PSRR high-order curvature-compensated BGR is discussed.

2 Design and Analysis of Proposed BGR

Fig.1 shows the proposed high-order curvaturecompensated BGR without LDO regulator in this paper. Compared to the conventional curvature-compensated BGR by adopting a piecewise-linear current，the proposed high-order curvature-compensated BGR without LDO regulator achieve a lower TC bandgap voltageVREFby adopting a piecewise-linear current and a current proportional 1.5 party to the absolute temperatureT．The operating supply voltage of the BGR shown in Fig.1 is the power supply voltageVDD，so the BGR shown in Fig.1 has a relative low PSRR in the low frequency.

Fig.1 Improved high-order curvature-compensated BGR without LDO regulator

To improve the PSRR performance of the proposed BGR in this paper，an improved high-PSRR high-order curvature-compensated BGR with LDO regulator is designed by adopting the technique of LDO regulator on the basis of the BGR circuit shown in Fig.1 and is shown in Fig.2.The proposed BGR with LDO regulator shown in Fig.2 consists of a bias circuit，a LDO regulator and a BGR core circuit.The function of the bias circuit will provide a reference voltage，which is independent of power supply voltage and is also the input voltage of LDO regulator.The BGR core circuit shown in Fig.2（c）is entirely the same as the BGR shown in Fig.1，but the operating supply voltage of the BGR core circuit shown in Fig.2（c）is the output voltageVREGof LDO regulator instead of power supply voltageVDD．Therefore，the proposed BGR with LDO regulator shown in Fig.2 will achieve a well PSRR performance than the BGR without LDO regulator shown in Fig.1.At the same time，the temperature performance of the BGR without LDO regulator shown in Fig.1 is similar to that of the BGR core circuit shown in Fig.2（c）.Therefore，to simplify the analysis of the proposed BGR，this paper will analysis and discuss performances of the proposed BGR with LDO regulator.

2.1 Design and Analysis of Proposed BGR Core Circuit

As shown in Fig.2（c），the BGR core circuit consists of transistorsM1-M19，transistorsMS1-MS6，resistorsR1-R5，PNP bipolar transistorsQ1-Q2and amplifiersA1-A2．Compared to the conventional piecewise curvature-compensated BGR，a current proportional 1.5 party to the absolute temperatureTis adopted in the proposed BGR core circuit，which is produced by transistorsM10-M17．In this paper，all MOS transistors adopt the long channel device so that the channel-length modulation effect is negligibly small.There are two possible equilibrium points in the BGR core circuit，so a start-up circuit is necessary.TransistorsMS1-MS6form the start-up circuits. AmplifiersA1andA2are entirely the same，and their dc gainAdhas thatAd?1．Bipolar transistorQ2has an emitter area which is m times that ofQ1．TransistorsM1andM2are entirely the same.AmplifierA1forces the voltages of nodeAand nodeBbe equal，i.e.VA＝VB＝VEB1．Here，VAandVBare the voltage of nodeAand nodeBrespectively，VEB1is the emitter-base voltage of bipolar transistorQ1．So，the drain currentI2of transistorM2can be expressed as

Fig.2 Improved high-order curvature-compensated BGR with LDO regulator

wherekis the Boltzmann’s constant；qis the electronic charge andTis the absolute temperature.Eq.（1）indicates thatI2is a current proportional to the absolute temperatureT．The width-length ratio of transistor M10isK1times that of transistor M2，so the drain currentI10of transistor M10has thatI10＝K1I2．Transistor M11operates in the saturation region and transistorM12operates in deep triode region.It is assumed that（W／L）11and（W／L）12are the width-length ratio of transistorsM11andM12respectively.Therefore，the drain-source resistancerds12of transistorM12can be expressed as

whereμnis electron mobility andCoxis unit area gateoxide capacitance.TransistorsM15andM16are entirely the same and they operate in the saturation region. TransistorsM13andM14operate in sub-threshold region and the channel width-length ratio ofM13isαtimes that ofM14．So the drain currents of transistorsM12-M16have thatI12＝I13＝I14＝I15＝I16．In fact，the drain currentIDof MOS operating in the sub-threshold region can be modeled as［28］

wherenis the sub-threshold slope factor；ID0is a process-dependent parameter；W／Lis the channel width-length andVGSis the gate-source voltage of MOS transistor.According to Eqs.（1）-（3），the drain currentI15of transistorM15can be derived as

Eqs.（4）and（5）indicate thatI15is a current proportional 1.5 party to the absolute temperatureT．TransistorsM15andM17form the current-mirror pairs，and the channel width-length ratio of transistorM17isK2times that of transistorM15．The drain currentI17of transistorM17has thatI17＝K2I15，so it is concluded thatI17is also a current proportional 1.5 party to the absolute temperatureT．AmplifierA2forces the voltages of nodeBand nodeCbe equal，i.e.VB＝VC＝VEB1．Here，VCis the voltage of nodeC．So，the drain currentI3of transistorM3can be expressed as

In Eq.（6），VEB1is a voltage with negative temperature coefficient，soI3is a current with negative temperature coefficient.TransistorsM2andM4are entirely the same.TransistorsM5andM6form currentmirror pairs，and the channel width-length ratio of transistorM6isK3times that of transistorM5．So，the drain currentI6of transistorM6has thatI6＝K3I2．The channel width-length ratio of transistorM7isK4times that of transistorM3，so the drain current of transistorM7has thatI7＝K4I3．

As shown in Fig.2（c），it can be obtained thatI6＝I7+I8＝I7whenTless than the reference temperatureTr1by optimizing the parameters ofK3andK4，hereI8is the drain current of transistorM8．TransistorsM8andM9form currentmirror pairs，and the channel width-length ratio of transistorM9isK5times that of transistorM8．So，the drain currentI9of transistorM9can be expressed as

Eq.（7）indicates thatI9is a current with piecewise-linear temperature coefficient.The aspect ratio of transistorM18isK6times that of transistorM3，so the drain currentI18has thatI18＝K6I3．The aspect ratio of transistorM19isK7times that of transistorM2，so the drain currentI19of transistorM19has thatI19＝K7I2．According to the above analysis，the output voltageVREFof the improved BGR shown in Fig.2 can be expressed as

whereVPTATandVCTATare a voltage with positive-and negative-temperature coefficient respectively；VNLis a voltage with piecewise-linear temperature characteristic andVPTAT1.5is a voltage proportional 1.5 party to the absolute temperatureT．Therefore，it is concluded that the weighted sum ofVPTATandVCTATcan form the conventional first-order bandgap voltage，as shown in Fig.3（a）.By adding voltagesVNLandVPTAT1.5into the output of BGR，the characteristics of the proposed BGR output voltageVREFcan be changed to Fig.3（b），and whose temperature drift will decrease.So，for the proposed BGR circuit shown in Fig.2，the temperature coefficient ofVREFwill become negligibly small by choosing appropriate values ofR1-R5，K0-K5，mand the width-length ratio of transistorsM11-M12in theory.

2.2 Analysis of Bias Circuit and LDO Regulator

As shown in Fig.2（a），the bias circuit will provide reference voltages of LDO regulator，and which is made up of transistorsMSS1-MSS4，MD1-MD5，resistorRD1-RD2and bipolar transistorQ0．The bias circuit has two possible equilibrium points，so a start-up circuit is required.The start-up circuit is made up of transistorsMSS1-MSS4．TransistorsMD1andMD2are entirely the same，and the width-length ratio of transistorMD4isMtimes that of transistorMD3．TransistorsMD2andMD5form current mirror pairs，so the drain voltageVBIASof transistorMD5can be expressed as

Fig.3 Relation curve of voltages VREF，VPTAT，VNLand VPTAT1.5.

where（W／L）D2，（W／L）D3and（W／L）D5are the widthlength ratio of transistorsMD2，MD3andMD5respectively andRBIASis the equivalent resistance seen from the drain of transistorMD5to ground.Eq.（8）indicates thatVBIASis independent of the power supply voltageVDD．

As shown in Fig.2（b），the LDO regulator consists of an error amplifier，a PMOS power transistorMD15and a feedback network.The feedback network consists of resistorsRFB1-RFB2and capacitorCD4．The error amplifier consists of transistorsMD6-MD14，resistorRD1and capacitorCD1，and which compare the reference voltageVBIASwith the feedback voltageVFBand provides an error voltage signalvgate．The error voltage signalvgatewill regulate the over-drive voltage of power transistorMD15and force the output voltageVREGof LDO regulator keep the correct voltage.So，the output voltageVREGof LDO regulator can be expressed as

According to Eqs.（8）and（9），it is concluded that the voltageVREGis also independent of the power supply voltageVDD．In fact，the LDO regulator can also be viewed as a feedback system consisting of a threestage amplifier driving a capacitive load，which is multiple-pole system.So，the open-loop stable of LDO regulator should be analyzed.To analyze the open-loop stable of LDO regulator，the equivalent topologic architecture of LDO regulator is shown in Fig.4.

Fig.4 Topologic architecture of LDO regulator

The conventional three-stage amplifier is made up of gain stagesAv1，Av2and power transistorMD15，which provides high dc gain.Gain stageAcand capacitorCD1form the damping-factor-control compensation stage. Gain stageAv1consists of transistorsMD6-MD10，and gain stageAv2consists of transistorsMD13-MD14．Gain stageAcconsists of transistorsMD11-MD12．gmd9，gmd11andgmd13are the equivalent input transconductance of gain stagesAv1，AcandAv2respectively.gmd15is the equivalent transconductance of power transistorMD15．ro1，ro2androfare the equivalent output resistance of gain stagesAv1，Av2，andAcrespectively.Co1andCo2are the equivalent parasitic capacitance at the output ofAv1andAv2respectively.CD1andCD2are compensation capacitor.RLis the equivalent load resistance，andCeq-out＝CD3+CL．Here，CLis the equivalent load capacitance.In order to analyze the stability of the LDO regulator，the following assumptions are made：（1）gmd（9，13）ro（1，2），gmd（9，11）rofandgmd15RL?1；（2）CD（1，2）andCeq-out?Co1；（3）Ceq-out?CD（1，2），Ceq-out?Co2andRFB（1，2）?RL．These assumptions simplify the transfer function without losing accuracy with the goal of providing a clearer insight into the designed structure.Based on the above assumptions，the loop small-signal transfer function of the LDO regulator can be expressed as

whereCD2-eq＝CD2+Co2．To cancel the effect of nondominant poles in the designed LDO regulator，the zerozfshould be placed lower frequency than the polesp1andpf，so the feedback resistorRFB2should be much smaller than feedback resistorRFB1．The effect of the polep1can be cancelled by the zerozfby optimizing transconductancegmd11，resistorRFB1and compensation capacitorsCD（1，4）．At the same time，CD1andCD4are the compensation capacitor，it is practical to take the assumption ofz1＜pfby optimizing compensation capacitorsCD（1，4）and resistorsRFB（1，2）．TransistorMD15is the power transistor and has a large channel widthlength ratio，so the zeroz2can be pushed to higher frequency than gain-bandwidth product（GBW）. Therefore，Eq.（10）can be approximated to

Eq.（11）shows that the loop transfer function of the designed LDO regulator is approximated to two poles system，so the phase margin（PM）can be approximately expressed by

whereGBW＝Adc×p-3dB．To ensure the stability of the designed LDO regulator，it should have a phase margin of at least 45°，with 60°preferable in most situations. Therefore，the polep2should be located at higher frequency than GBW，and the following expression can be given as

Fig.5 shows the simulated loop-frequency response of the designed LDO regulator.Simulation results show that the loop of LDO regulator achieves a phase margin of 58°，GBW of 12.16 MHz and dc gain of about 97.7 dB，which is sufficient to ensure the loop stability of LDO regulator.

Fig.5 Simulation open-loop frequency response of LDO regulator

2.3 Analysis of PSRR

As shown in Fig.2，the function of LDO regulator provides a stable output voltageVREGwhich is the operating supply voltage of the improved BGR core circuit instead of power supply voltageVDD．Compared to the proposed BGR without LDO regulator shown in Fig.1，the high-PSRR high-order curvature-compensated BGR shown in Fig.2 will achieve a well PSRR performance by adopting the LDO regulator，whose PSRR will be quantitatively analyzed as follows.

It is assumed that power supply voltageVDDhas an incremental voltage variationvddand there is an incremental voltage variationvregat the output of LDO regulator.For convenience，it is assumed thatgmj，rojandijare the transconductance，channel resistance and the small-signal drain current of transistorMjrespectively，herej＝1，2，…，19 andD1，D2，…，D15．Then，

TransistorsMD5andMD2form current-mirror pairs，and the channel width-length ratio of transistorMD5is theGtimes that of transistorMD2．Therefore，the incremental voltage variationvbiasat the gate of transistorMD8can be derived as

whereRbiasis the equivalent resistance seen from the drain of transistorMD5to ground.

At the same time，the output of LDO regulator has a variation voltagevreg，so the feedback voltage variationvfbcan be derived as

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As shown in Fig.2，transistorsMD6-MD14and compensation capacitorCD1form the error amplifier of LDO regulator，and it is assumed thatAeis the dc gain of the error amplifier andAe?1．Therefore，the gate voltage variationvgpassof power transistorMD15has thatvpgate≈Ae（vfb-vbias）．It is assumed thatRLeqis the equivalent resistance seen from the output of LDO regulator to ground.According to the Kirchhoff current law（KCL）at the output of LDO regulator，the relationvregandvddcan be derived as

At the same time，it is assumed thatva，vb，v1andv2are，respectively，the variation voltages of nodeA，nodeB，node 1 and node 2.TransistorsM1andM2are entirely the same，and their transconductance are equal，i.e.gm1＝gm2．AmplifierA1andA2are entirely the same，and their dc gainAdhas thatAd?1．So，va，vbandv1have thatva≈gm1（vreg-v1）ra，vb≈gm1（vregv1）rbandv1≈Ad（vb-va）．Here，raandrbare theequivalent resistor seen from nodeAand nodeBto ground respectively.Therefore，the small-signal currenti2of transistorM2can be derived as

In the similar way，the small-signal currenti3of transistorM3can be derived as

As shown in Fig.2，transistorsM2andM4are entirely the same.The channel width-length ratio of transistorM6isK3times that of transistorM5，and the channel width-length ratio of transistorM7isK4times that of transistorM3．The channel width-length ratio of transistorM9isK5times that of transistorM8，so the small-signal currenti9of transistorM9has thati9≈K5K3i2-K5K4i3．TransistorsM12-M15are long channel device.For the convenience of analysis，it is assumed that the channel-length modulation effect of transistorsM12-M15is negligibly small.The channel width-length ratio of transistorM10isK1times that of transistorM2．TransistorsM15andM17form current-mirror pairs，and the channel width-length ratio of transistorM17isK2times that of transistorM15．Therefore，the small-signal currenti17of transistorM17can be approximated to

The aspect ratio of transistorM19isK7times that of transistorM2，and the aspect ratio of transistorM18isK6times that of transistorM3．So，it is concluded thati19＝K7i2andi18＝K6i3．Here，i18andi19are the small-signal current of transistorsM18andM19respectively.It is assumed thatAdgm1（rb-ra）?1，Adgm3rc?1 andAdgm1rb?1．According to the circuit shown in Fig.2 and the above analysis，the relation ofvregand the output voltage variationvrefof proposed BGR can be derived as

So，the PSRR of the proposed BGR with LDO regulator shown in Fig.2 can be derived as

According to Eqs.（12）-（14），it is concluded that the PSRR of the proposed BGR with LDO regulator can efficiently be improved by adopting the technique of LDO regulator.

3 Simulation Results

The improved high-PSRR high-order curvaturecompensated BGR is designed and simulated in SMIC 0.18 μm CMOS process with a 1.8 V power supply voltage.

Fig.6 shows the simulated temperature property of high-order curvature-compensated BGR with-and without-LDO regulator.When temperature changes from-55℃to 125℃，the proposed high-PSRR highorder curvature-compensated BGR with LDO regulator achieves a temperature coefficient of 2.1×10-6／℃. And，the high-order curvature-compensated BGR without LDO regulator achieves a temperature coefficient of 2.54×10-6／℃.

Fig.6 Simulated temperature dependency of proposed BGR with-and without LDO regulator

Fig.7 shows the simulated PSRR of high-order curvature-compensated BGR with-and without-LDO regulator.The proposed high-order curvaturecompensated BGR with LDO regulator at 10 Hz，100 Hz，1 kHz，10 kHz，100 kHz and 1 MHz achieves the PSRR of-106.388，-106.388，-106.38，-105.93，-88.67 and-44.28 dB respectively.High-order curvature-compensated BGR without LDO regulator at 10 Hz，100 Hz，1 kHz，10 kHz，100 kHz and 1 MHz achieves the PSRR of -64.01，-64.01，-64，-63.5，-53.2 and -27.3 dB respectively.Simulation results show that the PSRR of high-PSRR high-order curvaturecompensated BGR with LDO regulator can efficiently be improved by adopting the technique of LDO regulator.

Fig.8 shows the simulated line-regulation of highorder curvature-compensated BGR with-and without-LDO regulator.When power supply voltageVDDchanges from 1.7 V to 2.5 V，the output voltageVREFof highorder curvature-compensated BGR with LDO regulator has only a deviation of about 3.92 μV，but the outputvoltageVREFof high-order curvature-compensated BGR without LDO regulator has a deviation of about 617.6 μV.Simulation results show that the proposed high-order curvature-compensated BGR with LDO regulator achieves a well line-regulation by adopting the technique of LDO regulator.

Finally，the performances of high-PSRR highorder curvature-compensated BGR are summarized in Table 1.As shown in Table 1，the temperature coefficient of the improved high-PSRR high-order curvature-compensated BGR in this paper has a commensurate level with those BGRs reported in Refs.［6，14，26-27］.However，by adopting the technique of LDO regulator in this paper，the improved high-PSRR high-order curvature-compensated BGR achieves well performance of PSRR and line-regulation than those reported in Refs.［6，14，26-27］.

Fig.7 Simulated PSRR of proposed BGR with-and without LDO regulator

Fig.8 Simulated line-regulation of proposed BGR withand without LDO regulator

Table 1 Performance summary of BGR

4 Conclusions

A high-PSRR high-order curvature-compensated BGR is designed and analyzed by adopting a LDO regulator and two kinds of current which are a piecewise-linear current and a current proportional 1.5 party to the absolute temperatureT．respectively.Low TC is achieved by adopting two kinds of currents including a piecewise-linear current and a current proportional 1.5 party to the absolute temperatureT．The high-PSRR performance is achieved by adopting the LDO regulator whose output voltage is the operating supply voltage of BGR core circuit instead of power supply voltageVDD．Simulation results show that the improved high-PSRR high-order curvature-compensated BGR with LDO regulator achieves an output voltage with excellent stability，a low TC and high PSRR performance.It is well suited for analogue and mixed signal electronic systems.

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TN432

：

：1005-9113（2015）05-0116-09

10.11916／j.issn.1005-9113.2015.05.018

2014-07-10.

Sponsored by the National Natural Science Foundation of China（Grant No.61471075），the 2013 Program for Innovation Team Building at Institutions of Higher Education in Chongqing（The Innovation Team of Smart Medical System and Key Technology）.

?Corresponding author.E-mail：zhouqn＠cqupt.edu.cn.