摘要:為消除運(yùn)算放大器失調(diào)電壓對帶隙電壓精度的影響,采用NPN型三極管產(chǎn)生ΔVbe,并設(shè)計(jì)全新的反饋環(huán)路結(jié)構(gòu)產(chǎn)生了低壓帶隙電壓.電路采用 SMIC 0.18 μm CMOS工藝實(shí)現(xiàn),該新型低壓帶隙基準(zhǔn)源設(shè)計(jì)輸出電壓為0.5 V,溫度系數(shù)為8 ppm/℃,電源抑制比達(dá)到-130 dB,并成功運(yùn)用于16位高速ADC芯片中.
關(guān)鍵詞:帶隙基準(zhǔn)電壓源;低壓;正溫度系數(shù);負(fù)溫度系數(shù);電源抑制比
中圖分類號:TN402 文獻(xiàn)標(biāo)識碼:A
參考文獻(xiàn):
[1] BECKERGOMEZ A,LAKSHMI VISWANATHAN T,VISWANATHAN T R. Lowsupplyvoltage CMOS subbandgap reference[J]. IEEE Journal of Circuits and SystemsⅡ, 2008, 55(7): 609-613.
[2] DEVITA G,IANNACCONE G. A Sub1V, 10 ppm/℃, nanopower voltage reference generator[J]. IEEE Journal of SolidState Circuits, 2007, 42(7):1536-1542.
[3] NEUTEBOOM H,KUP B M J,JANSSENS M. A DSPbased hearing instrument IC[J]. IEEE Journal of SolidState Circuits, 1997, 32(11): 1790-1806.
[4] BANBA H,SHIGA H,UMEZAWA A,et al.A CMOS bandgap reference circuit with Sub1V peration [J].IEEE Journal of SolidState Circuits,1999,34(5):670-674.
[5] ANNEMA A J. Lowpower bandgap references featuring DTMOSTS[J]. IEEE Journal of SolidState Circuits,1999,34(7):949-955.
[6] ALLEN P E, HOLBERG D R. CMOS analog circuit design [M].2nd ed.New York: Oxford University Press,2002:153-156.
[7] MALCOVATI P,MALOBERTI F,PRUZZI M,et al.Curvaturecompensated BiCMOS bandgap with 1V supply voltage[J]. IEEE Journal of SolidState Circuits,2001,36(7):1076-1081.
[8] KER Mingdou,CHEN Jungsheng,CHU Chingyun. A CMOS bandgap reference circuit for sub 1V operation without using extra lowthreshold voltage device[J]. IEEE Journal of Circuits and Systems,2004,2150-2155.