基于遞歸通用信號(hào)延遲疊加算子的單相鎖相環(huán)

劉 勇，楊 濤，盤宏斌，曾 力，曹 雷

基于遞歸通用信號(hào)延遲疊加算子的單相鎖相環(huán)

劉 勇1，楊 濤1，盤宏斌1，曾 力1，曹 雷2

(1.湘潭大學(xué)自動(dòng)化與電子信息學(xué)院，湖南 湘潭 411105；2.貴州電網(wǎng)有限責(zé)任公司都勻供電局，貴州 都勻 558000)

當(dāng)電網(wǎng)電壓存在諧波與直流偏移時(shí)，傳統(tǒng)鎖相環(huán)無法精確鎖相。為此，提出一種基于遞歸通用信號(hào)延遲疊加算子的改進(jìn)單相鎖相環(huán)算法。該方法在鎖相環(huán)前級(jí)引入遞歸通用信號(hào)延遲疊加算子，以產(chǎn)生正交信號(hào)并濾除諧波。接著在兩相靜止坐標(biāo)系下，構(gòu)建延遲采樣周期濾波器，通過將正交分量延遲兩個(gè)采樣周期的方法抑制直流偏移。所提單相鎖相環(huán)技術(shù)能夠消除直流偏移和諧波干擾的影響，快速準(zhǔn)確地獲取基波和所需的特定次諧波信息，同時(shí)具有良好的動(dòng)態(tài)性能和穩(wěn)定性。最后，仿真與實(shí)驗(yàn)結(jié)果證明了該方法的可行性。

單相鎖相環(huán)；延遲信號(hào)疊加；直流偏移；諧波分離；同步信號(hào)檢測

0 引言

在有源電力濾波器和分布式發(fā)電系統(tǒng)等能源和電力應(yīng)用中，快速準(zhǔn)確地獲取電網(wǎng)電壓的相位、頻率和諧波成分等信息是十分重要的[1-4]。鎖相環(huán)結(jié)構(gòu)(Phase-Locked Loop, PLL)由鑒相器、環(huán)路濾波器和壓控振蕩器組成，結(jié)構(gòu)簡單、易于實(shí)現(xiàn)，被廣泛應(yīng)用于電網(wǎng)同步[5-9]。

不同于三相供電系統(tǒng)，在單相系統(tǒng)中，由于只有一個(gè)輸入信號(hào)，鎖相環(huán)結(jié)構(gòu)更為復(fù)雜[10]。近年來，基于正交信號(hào)發(fā)生器(Quadrature Signal Generator, QSG)的鎖相環(huán)因其在非理想電網(wǎng)電壓條件下的魯棒性，在單相系統(tǒng)中發(fā)揮著至關(guān)重要的作用[11-14]。

文獻(xiàn)[15]詳細(xì)研究了包括二階廣義積分器(Second-Order Generalized Integrator, SOGI)以及復(fù)系數(shù)濾波器(Complex-Coefficient Filter, CCF)在內(nèi)的多種正交信號(hào)發(fā)生技術(shù)。這些方法通過單相電網(wǎng)電壓信號(hào)生成虛擬正交信號(hào)，具有動(dòng)態(tài)響應(yīng)慢、對(duì)諧波敏感等缺點(diǎn)。文獻(xiàn)[16]推導(dǎo)了一種通用信號(hào)延遲疊加算子(Generalized Delayed Signal Superposition Operator, GDSS)，GDSS算子能夠?qū)崿F(xiàn)對(duì)單相輸入信號(hào)中任意所選頻率信號(hào)的提取，并生成其對(duì)應(yīng)的正交信號(hào)?；谶@種GDSS算子，文獻(xiàn)[17]提出了一種基于GDSS算子的鎖相環(huán)結(jié)構(gòu)(GDSS-PLL)，可以在諧波干擾下快速準(zhǔn)確地提取基波及諧波信號(hào)同步信號(hào)。

在實(shí)際電網(wǎng)中，由于電網(wǎng)故障、數(shù)字信號(hào)處理器中的 A/D 轉(zhuǎn)換、地磁現(xiàn)象、半波整流、電流互感器飽和以及分布式發(fā)電系統(tǒng)的直流注入等原因[18-19]，PLL輸入電壓中會(huì)產(chǎn)生直流偏移。而直流偏移會(huì)導(dǎo)致PLL輸出波形中含二倍頻波動(dòng)[20]。文獻(xiàn)[21]給出了直流偏移對(duì)鎖相環(huán)性能影響的定量分析。結(jié)果表明，隨著前級(jí)輸入中直流偏移量的增大，鎖相環(huán)的帶寬必須相應(yīng)減小。

針對(duì)以上問題，本文在GDSS-PLL的基礎(chǔ)上，提出一種改進(jìn)單相鎖相環(huán)技術(shù)。首先，在離散域下基于直接形式的GDSS算子推導(dǎo)GDSS算子的遞歸實(shí)現(xiàn)形式。相對(duì)直接形式GDSS算子而言，遞歸GDSS算子減小了實(shí)現(xiàn)復(fù)雜度，且降低了計(jì)算量。然后，提出了一種延遲采樣周期濾波器(Delay Sampling Period Filter, DSPF)以濾除PLL輸入中的直流偏移。并對(duì)所提DSPF算法的抗噪性能進(jìn)行研究，給出了相應(yīng)的解決方案。接著，通過遞歸GDSS算子提取單相輸入信號(hào)中的基波及所需諧波信號(hào)，并生成其對(duì)應(yīng)的正交信號(hào)。同時(shí)引入DSPF濾除所得信號(hào)中的直流偏移。最后通過基于同步旋轉(zhuǎn)坐標(biāo)系的鎖相環(huán)(Synchronous Reference Frame-Phase Locked Loop, SRF-PLL)獲取電網(wǎng)基波頻率和相位信息。仿真與實(shí)驗(yàn)結(jié)果表明，所提鎖相方法在不同電網(wǎng)故障下都能保持良好的同步性能。

1 通用信號(hào)延遲疊加算子

1.1 濾波原理介紹及推導(dǎo)

文獻(xiàn)[16]提出一種GDSS算子，其表達(dá)式為

根據(jù)文獻(xiàn)[26]給出的三角函數(shù)疊加公式，可以將式(4)進(jìn)一步簡化為

圖1 GDSS直接實(shí)現(xiàn)形式

Fig. 1 Direct-form of GDSS

1.2 遞歸實(shí)現(xiàn)形式

其中，j為虛部，根據(jù)式(11)，式(9)和式(10)可以進(jìn)一步簡化為

圖2 GDSS遞歸實(shí)現(xiàn)形式

進(jìn)一步推導(dǎo)，式(14)和式(15)可表示為

表1 RGDSS參數(shù)表

2 直流偏移濾除方法

根據(jù)式(19)和式(20)，通過推導(dǎo)可得次諧波在軸上的分量，可表示為

在工程實(shí)際中，DSPF算法需要在離散域內(nèi)實(shí)現(xiàn)，對(duì)式(21)和式(22)進(jìn)行離散化。

所提DSPF算法可以濾除直流偏移，理論動(dòng)態(tài)響應(yīng)時(shí)間僅為兩個(gè)采樣周期。與目前廣泛應(yīng)用的DSC算法相比，動(dòng)態(tài)響應(yīng)時(shí)間明顯縮短。

從圖4可以看出，基波頻率和相位同步是通過SRF-PLL實(shí)現(xiàn)的，但其性能主要由GDSS算子和DSPF模塊所組成的前置濾波級(jí)決定。因此可以根據(jù)具體應(yīng)用和控制要求靈活設(shè)計(jì)GDSS算子和DSPF模塊的參數(shù)和個(gè)數(shù)。由于預(yù)濾波級(jí)的RGDSS和DSPF模塊濾除了諧波和直流偏移，輸入信號(hào)沒有失真，因此SRF-PLL的帶寬可以設(shè)置的足夠?qū)?，PI參數(shù)可以按照文獻(xiàn)[29]所述設(shè)計(jì)。

圖4 MRGDSS-DSPF-PLL結(jié)構(gòu)圖

3 仿真結(jié)果分析

為進(jìn)一步檢驗(yàn)MRGDSS-DSPF-PLL的動(dòng)態(tài)性能和穩(wěn)定性，設(shè)置了電壓跌落、相角跳變和頻率跳變3種工況。

圖6 在直流偏移和諧波干擾下的仿真結(jié)果

圖7 電壓跌落的仿真結(jié)果

圖8 相角跳變的仿真結(jié)果

圖9 頻率跳變的仿真結(jié)果

4 實(shí)驗(yàn)結(jié)果分析

本文實(shí)驗(yàn)基于StarSim半實(shí)物平臺(tái)進(jìn)行驗(yàn)證，如圖10所示，實(shí)驗(yàn)平臺(tái)主要由快速控制原型器、I/O信號(hào)轉(zhuǎn)接板、實(shí)時(shí)仿真器以及主機(jī)操控平臺(tái)組成。通過基于FPGA的實(shí)時(shí)仿真器模擬單相電壓信號(hào)，鎖相環(huán)算法經(jīng)過編譯后下載到快速控制原型器中運(yùn)行，鎖相結(jié)果可通過示波器或上位機(jī)顯示。實(shí)驗(yàn)中參數(shù)設(shè)置與仿真一致，實(shí)驗(yàn)結(jié)果如圖11所示。

圖10 半實(shí)物平臺(tái)組成

所提單相鎖相環(huán)在直流偏移和諧波干擾下的實(shí)驗(yàn)結(jié)果如圖11(a)所示。對(duì)比圖6仿真結(jié)果以及圖11的實(shí)驗(yàn)結(jié)果，動(dòng)態(tài)過程超調(diào)量和響應(yīng)時(shí)間基本一致，可以看出所提方法能夠?qū)崿F(xiàn)基波頻率快速準(zhǔn)確的估計(jì)，由RGDSS和直流偏移濾除算法所組成的前置濾波級(jí)可以有效且快速地消除直流偏移和諧波干擾的影響，進(jìn)而使SRF-PLL成功鎖相。

圖11(b)是電壓跌落時(shí)鎖相環(huán)的輸出波形，可以看到鎖相環(huán)動(dòng)態(tài)響應(yīng)時(shí)間較短，約25 ms時(shí)鎖相環(huán)輸出達(dá)到穩(wěn)定，且頻率波形超調(diào)也較小，約為4%，與仿真結(jié)果相吻合。圖11(c)是相角跳變時(shí)的實(shí)驗(yàn)結(jié)果，由于加入了DSPF算法，頻率估計(jì)過程超調(diào)量較大。頻率突變時(shí)的實(shí)驗(yàn)結(jié)果如圖11(d)所示，在頻率偏移情況下鎖相環(huán)仍能準(zhǔn)確估計(jì)頻率。實(shí)驗(yàn)證明了所提單相鎖相環(huán)結(jié)構(gòu)在電網(wǎng)常見故障下仍能精準(zhǔn)鎖相，盡管DSPF算法會(huì)增大頻率估計(jì)時(shí)動(dòng)態(tài)響應(yīng)的超調(diào)量，但能通過調(diào)節(jié)使其表現(xiàn)出滿意的性能。

圖11 實(shí)驗(yàn)結(jié)果

5 結(jié)論

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Single-phase phase-locked loop based on recursive implementation of generalized delayed signal superposition

LIU Yong1, YANG Tao1, PAN Hongbin1, ZENG Li1, CAO Lei2

(1. School of Automation and Electronic Information, Xiangtan University, Xiangtan 411105, China;2. Duyun Power Supply Bureau, Guizhou Power Grid Co., Ltd., Duyun 558000, China)

When there are harmonics and DC offset in a grid voltage, the traditional phase-locked loop (PLL) cannot accurately realize phase lock. Hence, an improved single-phase phase-locked loop algorithm based on recursive-form generalized delayed signal superposition (RGDSS) operators is proposed. To produce the orthogonal signals and filtering of the harmonic, RGDSS operators are introduced into the pre-stage of the PLL. Then in a two-phase stationary reference frame, a delayed sampling period filter is constructed to suppress the DC offset by delaying the orthogonal component by two sampling periods. The proposed PLL, which has good dynamic performance and stability, can effectively eliminate the influence of DC offset and harmonics, and obtain the fundamental and desired harmonic information quickly and accurately. Finally, the feasibility of the method is verified by simulation and experiment.

single-phase phase-locked loop; delayed signal superposition; DC offset; harmonic separation; detection of synchronizing signal

10.19783/j.cnki.pspc. 211175

國家自然科學(xué)基金項(xiàng)目資助(51577162)；湖南省自然科學(xué)基金項(xiàng)目資助(2021JJ30674)

This work is supported by the National Natural Science Foundation of China (No. 51577162).

2021-08-27；

2021-12-28

劉 勇(1976—)，男，碩士，副教授，研究方向?yàn)槲⒕W(wǎng)穩(wěn)定性和新能源微網(wǎng)逆變器；E-mail: xtdx_ly@163.com

楊 濤(1995—)，男，通信作者，碩士研究生，研究方向?yàn)樾履茉床⒕W(wǎng)鎖相環(huán)技術(shù)；E-mail: 2945185118@qq.com

盤宏斌(1972—)，男，博士，教授，研究方向?yàn)榭稍偕茉窗l(fā)電與并網(wǎng)技術(shù)。E-mail: pan_hongbin@xtu.edu.cn

(編輯 許 威)