Time-Efficient Identification Method for Aging Critical Gates Considering Topological Connection

Tian-Song Yu, Hua-Guo Liang, Da-Wen Xu, and Lu-Sheng Wang

Time-Efficient Identification Method for Aging Critical Gates Considering Topological Connection

Tian-Song Yu, Hua-Guo Liang, Da-Wen Xu, and Lu-Sheng Wang

—The shrinking silicon feature size causes the continuous increment of the aging effect due to the negative bias temperature instability (NBTI), which becomes a potential stopper for IC development. As the basis of circuit-level aging protection, an efficient aging critical-gate identification method is crucially required to select a set of gates for protection to guarantee the normal lifetime of the circuits. The existing critical-gate identification methods always depend on a critical path set which contains so many paths that its generation procedure requires undesirable CPU runtime; furthermore, these methods can achieve a better solution with taking account of the topological connection. This paper proposes a time-efficient critical gates identification method with topological connection analysis, which chooses a small set of critical gates. Experiments over many circuits of ITC99 and ISCAS benchmark demonstrate that, to guarantee the normal lifetime (e.g., 10 years) of each circuit, our method achieves a 3.97x speedup and saves as much as 27.21% area overhead compared with the existing methods.

Index Terms—Aging critical gates, negative bias temperature instability, topological connection.

1. Introduction

As the CMOS technology aggressively scales, the reliability degradation is emerging as a serious challenge for integrated circuits. The aging effect due to the negative bias temperature instability (NBTI) can cause more than 20% degradation of circuit performances at the worst case over a period of ten years[1]-[3], and it has become one of the most critical reliability concerns for digital circuits in the nanometre process[4],[5]. As aging becomes increasingly serious, several typical techniques, which include input vectors control (IVC)[6],[7], gate replacement (GR)[8], and adaptive voltage scaling (AVS)[9]-[11], were proposed to mitigate the aging effect. However, the efficiency of these techniques is restricted more or less by the process of aging critical gates (CGs) identification.

Critical gates are the most important nodes for timing degradation in the lifetime of a circuit. The identification of CGs, as the basis of aging-protection techniques, which are crucial to enhance the reliability for high-performance integrated circuit, is key work for the reliable IC design. However, the existing methods of CGs identification all depend on critical paths set (CPS), which requires huge CPU runtime to generate the CPS due to the exponential explosion of the number of paths in the circuit[12], i.e., it takes more than ten hours to generate a critical path set for s15850[13],[14]. The CPS generation consumes so much CPU runtime that it would seriously extend the development cycle of digital chip design. Moreover, the existing CGs identification methods could be further optimized by considering the topological connection.

As the CGs identification is critical work for mitigating circuit aging[6],[7],[15], several methods have been proposed. W. Wang et al. proposed an approach for CGs searching relied on CPS with handling each path in the CPS, and then the CGs could be abstracted[16]. Y. Cao et al. proposed a method for CGs identification based on the consideration of the node criticality in the circuit[17]. Both of them were required to generate CPS as an input, however, it was extremely time-dependent work for its exponential complexity, even in small-size circuits. Moreover, they did not take account of the topological connection.

The correlated paths are mainly caused by the shared nodes in the circuit as illustrated in Fig. 1. The critical paths in the circuit are generally highly correlated, which means that amounts of them will share one or more gates[12],[13]. The topological connection among logic gates (TCLG) in circuits stands for whether two gates locate at the same paths (at least two paths). If two gates are at the same path, they have the topological connection. For example, G1 and G10 are on the same path. G1 can arrive at the G10 passing through several gates (G2 and G3) on different topological levels. But it cannot arrive at some gates such as G5, G6, and G7. Hence, the topological connection exists between G1 and G10. If two more paths are correlated, the topological connection appears among the shared gates. Suppose that there are six critical paths in a circuit, asshown in Fig. 1, it is evident that they are correlated with the shared node G10. Protecting G10 could mitigate the aging effect of the six critical paths but protecting other gates could not do. So the analysis of the shared gates seems to be crucial for the CGs identification in a circuit. However, so far, all the existing methods for identifying the CGs did not consider the topological connection of logic gates in the circuit, which was caused by the shared logic gates.

Fig. 1. Example of correlated paths.

In this paper, the TCLG in a circuit is analyzed and taken into account in the process of CGs identification. We propose a time-efficient method for CGs identification taking account of the circuit topological connection. The contributions of this paper can be summarized into the following aspects.

· A time-efficient identification method for CGs is proposed with considering the circuit topological connection. It can abstract the specific gates set which has the most critical effect on the whole circuit.

· An algorithm for CGs identification is proposed without depending on the CPS, which greatly reduces the searching time.

The rest of this paper is organized as follows. Section 2 describes the related work. Section 3 gives the NBTI effect and models. Section 4 proposes our identification method for CGs. Section 5 shows our experimental results on ITC99 and ISCAS benchmark circuits. Section 6 gives the conclusions of this paper.

2. Related Work

CGs protection is the main approach for mitigating circuit aging. In [6] and [7], IVC techniques were proposed for aging protection. When the circuit was on standby mode, specific input vectors were applied to the circuit inputs to mitigate the aging effect. D. Bild et al. proposed an internal node control (INC) technique which could permit much more control of all levels in the circuit to decrease the NBTI-induced delay[18]. Y. Wang et al. proposed two gate replacement algorithms together with optimal input vector selection to reduce the leakage power and mitigate the NBTI-induced degradation[8]. Most of CGs in the circuit would be abstracted under protection in the standby mode by using gate replacement technique. Like the method proposed in [15], I. C. Lin et al. proposed a novel transmission gate-based technique to minimize the NBTI-induced degradation and leakage. It inserted a transmission gate and a pull up device in front of the critical gate, forcing one input of the critical gate to a high level in the standby mode to mitigate the static NBTI effect.

Fig. 2. CGs identification flow.

All the techniques mentioned above illustrate that the CGs identification is the most critical basis for mitigating the circuits aging. Fig. 2 shows the principal steps of the existing CGs identification methods. W. Wang et al. proposed an efficient CGs identification method relying on CPS[16]. Firstly, the static timing analysis (STA) was applied into an original circuit without considering the NBTI. Given the timing constraint for the circuit paths, the potential critical paths (PCPs) could be abstracted. Moreover, the CPS would be obtained from the PCPs with considering the NBTI effect. The CGs could be abstracted by making every path in the CPS meet the timing requirement by using the gate replacement technique.

In [17], the node criticality computation for circuit timing analysis was proposed. It defined the node criticality for the logic gate in the circuit. The potential critical paths were obtained by STA just like in [16]. The longest path in PCPs was called the most critical path (MCP). Given a node ni, two different node criticality computations were defined based on whether the node located at the MCP or not. After finishing the criticality computations for all gates, they were ordered according to the degree of their degradations. The CGs could be also abstracted by optimizing the circuit using gate replacement technique.

Fig. 3. CGs identification for correlated paths.

The method in [16] was the primary approach for CGs identification. Unfortunately, it did not take the TCLG into consideration in the circuit, which could make some critical paths over protected and the CPU runtime for the CPS generation extremely huge. As an example for CGs identification for correlated paths illustrated in Fig. 3, there are four critical paths in the circuit: {P1: G1-＞G2-＞G3-＞G4-＞G10-＞G11, P2: G1-＞G2-＞G3-＞G4-＞G8-＞G9, P3: G5-＞G6-＞G7-＞G4-＞G8-＞G9, P4: G5-＞G6-＞G7-＞G4-＞G10-＞G11}. We assume that G3 and G11 are the critical gates in the path P1 abstracted using the method in [16]. Two paths may share the same gate and wire. As shown in Fig. 3, P1 shares gate G4 with P2. Once G4 becomes a critical gate in the path P2, P1 would be over-protected. As amounts of the correlated paths exist in the circuit, mitigating the aging effect by replacing thecritical gates which are generated by the method in [16] could make some critical paths over-protected. Moreover, the CPS generation is an extremely time-consumed work.

In this paper, a novel CGs identification method considering the TCLG (CGIMT) is presented. Unlike the existing methods, this approach can efficiently capture the impact of the topological correlation among the logic gates in the circuit for CGs identification.

3. NBTI Effect and Models

When a negative bias voltage (Vgs= -Vdd) is applied to a PMOS device, causing a shift in the threshold voltage, the NBTI effect occurs. On the contrary, when a positive bias voltage (Vgs=0) is applied to the PMOS device, the shifted Vth could be partly recovered. Fig. 4 shows the two conditions of a PMOS device with different Vgs[19].

Fig. 4. Cross section of a PMOS decice under two conditions: (a) stess and (b) recovery.

NBTI stress: When the gate voltage Vgof the PMOS transistor applies a low level (Vgs= -Vdd), it is on the stress condition. At this time, holes from the inversion layer can break the Si-H bonds, creating interface traps and neutral H atoms. Then, the H atoms convert into H2molecules. When H2molecules diffuse away, interface traps are left. When interface traps accumulate between silicon and the gate oxide interface, they cause a shift in the threshold voltage.

Recovery: In the recovery phase, when the biased voltage is removed, the reverse reaction is performed. Some hydrogen diffuses back toward the interface and bonds with Si, which reduces the number of interface traps and the NBTI effect. Although the recovery phase can reverse the NBTI effect, it does not eliminate all the interface traps generated during the stress phase, and the PMOS threshold voltage will increase in the long term.

S. Bhardwaj et al. proposed a long term model which provided an accurate and efficient estimate of the long term threshold voltage degradation of the PMOS due to the NBTI[4]. The voltage variation of a PMOS transistor ΔVth due to the NBTI at time t can be expressed as

where n is the time exponent, Kvis a constant related to device parameters, Tclkis the clock cycle, α is the duty cycle (i.e., the ratio of total stress time to total operating time). βtis a time-dependent parameter expressed as follow:

where ξ1, ξ2, and C are constants, toxis the oxide thickness of the PMOS device, t is the working time, and teis a constant determined by the working time.

Parameters variation of PMOS devices caused by the NBTI effect will lead to the augment of gate delay. Meanwhile, the delay of data paths would increase and timing violation occurs when the delay increases to a certain threshold value. Y. Cao et al. proposed a gate delay computing model based on the long term NBTI prediction model. It is expressed as

where a0iis the intrinsic delay of the gate without NBTI effect and a1iis a constant, these two parameters can be obtained by Hspice simulation. In this work, we use a 65 nm PTM[20]model in Hspice simulation to extract the delay information for different style gates at a discrete time unit. By fitting the simulation results with (3), we can get the coefficient values for a0iand a1i.

4. CGs Identification Approach

This section demonstrates that our CGs identification method is different from the existing methods. Its framework is illustrated in Fig. 5 which demonstrates the main steps for the proposed scheme. The PCGs and CGs generation are described in Sections 4.2 and 4.3. Finally, an algorithm is proposed to capture the impact of the topological connection among the logic gates in the circuit for CGs identification.

4.1 Framework of CGIMT

In this paper, there are three steps for the CGs identification as shown in Fig. 5.

Step 1 (PCGs generation): In this step, we parse the given circuit and then get its topological structure. And then we set the intrinsic delay and delay degradation to be a certain value respectively for every gate in the circuit. As we know, the signal probability α is an important parameter for the circuit aging prediction when the work time is a constant. In [16], the path delay degradation was expressed as a function of α. To make a path get the worst delay degradation, a certain value of α could be calculated. But itseems to be not impractical. In [21], all the gates were stressed with the signal probability fixed as 0.95 to predict the circuit aging. However, it seems to be pessimistic. The signal probability was set to be 0.5 in [22] and [23] for all gates in the circuit. In this paper, we fix α as 0.5 with NBTI-stress for ten years. After analysing the aging state of every gate in the circuit, PCGs could be generated.

Fig. 5. Framework of the CGIMT.

Fig. 6. CGs generation considering TCLG: (a) PCGs, (b) analysis of the PCGs, and (c) gates for replacement.

Step 2 (get the gates for replacement): After the PCGs generation is finished in Step 1, the connections among the gates in PCGs should be abstracted. And then the new topological structure for PCGs would be obtained. We can get the gates for replacement by the proposed algorithm with considering TCLG.

Step 3 (aging test and CGs generation): After replacing the abstracted gates, a new netlist of circuit will be generated. Then aging test would be applied to the new circuit. If the aging test is successful, the replaced gates are aging critical gates.

4.2 PCGs Generation

After parsing the given circuit, its topological structure is obtained and the aging parameter of every gate could be initialized. Suppose that Gi is a gate in a given circuit, the processes of PCGs generation are introduced as follows.

We can abstract the longest path Pi which contains Gi in a high speed as the circuit is on topological sort. By travelling the circuit forward and reverse, the delay degradation Tiand the intrinsic delay tiwithout considering NBTI of Pi could be obtained. Additionally, the maximum intrinsic delay for all paths in the circuit expressed as D0could be acquired. Supposed that q% is timing margin, the slack of Pi can be expressed as (1+q%)-ti. Furthermore, the delay degradation contribution Cvof Gi for Pi can be computed by CV=ΔdGi/slack, where ΔdGiis the delay degradation of Gi. If the inequation Ti＞D0(1+q%) and Cv＞p% are simultaneously satisfied, Gi would be put into PCGs. After dealing with all the gates in circuit, PCGs generation is finished.

In this work, Pw is the path which has the maximum delay degradation among all the longest paths in the circuit. Then, we can give a solution for computing the value of p% expressed as following

where Dagingis the aging delay while Dwis the intrinsic delay of Pw, and N is the gates number of Pw.

4.3 CGs Generation

As the PCGs generation has been finished in Section 4.2, every gate Gi in the PCGs has two features: One is that the longest path Pi which contains Gi experiences timing violation and the other is that it ages seriously. In this part, we abstract the critical gates from the PCGs with considering topological connection among the gates by utilizing the proposed algorithm.

Fig. 6 illustrates the workflow of CGs generation. Suppose that the PCGs contains nine gates, as shown in Fig. 6 (a), all of them seem to be individual. Actually, the topological connections exist among the potential critical gates and we characterize them by the dotted lines as demonstrated in Fig. 6 (b). Then the topological connections among the potential critical gates can be easily understood from Fig. 6 (b). For example, the gate a could arrive at the gate c passing though amounts of logic gates (do not appear in Fig. 6 (b)) on different topological levels.

Moreover, one gate would have different criticality for aging degradation in a circuit. As illustrated in Fig. 6 (b), the gate e which connects with all the gates in the PCGs seems to be more crucial to the whole circuit than others. Additionally, the gates c and g have the same feature. We can abstract a series of gates as shown in Fig. 6 (c) for replacing by analysing this feature. After the aging test receives a success, the critical gates could be obtained. As the TCLG is a crucial factor identifying the CGs mentioned above, we define the criticality for the gates in the PCGs expressed as

where TMGiis a parameter evaluating the degree of topological connection for Gi in PCGs, ΔdGiis the delay degradation for Gi. The Gi is more critical with a bigger WGicompared to other gates.

Fig. 7. CGs identification algorithm.

In order to extract the CGs from PCGs, an algorithm with considering the TCLG is presented as illustrated in Fig. 7. Firstly, we define a parameter TM for every gate in the PCGs and initialize it with an initial value 0 (lines 1-3). After initializing the PCGs, we would obtain the TM for all the gates in the PCGs (lines 4-5). For each gate gi, we search every gate Gj that gi can arrive at (lines 6-7). As for Gj, if it can be found in the PCGs (suppose that gj is the gate), both the TM of gi and gj would plus 1 (lines 8-10). Afterwards, we can upload the delay degradation and the Wgifor every gate in the PCGs (lines 11-13). Furthermore, we sort the gates in the PCGs by the value Wgi(line 14). We replace the gate with a bigger Wgiand store them in the CGs after finishing the circuit aging protection (lines 16-19).

Complexity: In this algorithm, as each gate in the original circuit is evaluated by the topological order, the complexity is O (M×N), where M is the number of PCGs and N is the total number of the circuit gates.

5. Experiments

5.1 Implementation

In this paper, we implement the CGs identification algorithm by C++ in VS2010. The intrinsic delay a0iand the coefficient a1iin (3) are fitted by HSPICE simulation. The experiments are applied to nine benchmark circuits from ITC99 and ISCAS. The time margin is set to be 7%. The circuit lifetime is set to 10 years. Some critical technology parameters are: Vdd=0.9 V, |Vth|=0.365 V for both PMOS and NMOS transistors, the thickness of oxide tox=1.2 nm. The active time temperature T is set as 378 K.

5.2 Results and Discussion

The accuracy of aging analysis is an important target for aging prediction. In order to prove the accuracy of our proposed scheme, we assign l000 random input vectors to the circuit to simulate the “real” aging-induced degradation. And then we compare our prediction and existing prediction on circuit aging with the real aging prediction (RAP). We analyse 100 critical paths chosen in random from each experimental circuit and utilize their aging conditions to characterize the aging state of each circuit approximately. Fig. 8 shows the experimental results on nine benchmark circuits from ITC99 and ISCAS. Experimental results show that our scheme could achieve a better matching compared with RAP than the method in [16]. The difference between our scheme and the RAP is less than 0.32% on average as illustrated in Fig. 8.

Fig. 8. Aging prediction for circuits.

Fig. 9 demonstrates the number of CGs generated by the method in [16] and the method proposed in this paper with the timing margin q% obtaining the same value. As shown in Fig. 9, with taking the TCLG into account, the number of CGs generated by our method is less than that in [16]. Experiments in Fig. 8 also illustrate that the number of the critical gates generated by the CGIMT is less than 33.82% compared with the [16] on average.

Even though our scheme can abstract less number of critical gates, the area overhead may be unacceptable. The area overhead stands for the area increment of the circuit after replacing the critical gates. In order to clarify this problem, we evaluate the area overhead of them. Fig. 10 is the evaluation results of the area overhead on the experimental circuits. Experimental results of the area overhead on the benchmark circuits reveal that our method can save as much as 27.21% area on average.

Moreover, the CPU runtime, as illustrated in Fig. 11, has greatly induced compared with the method in [16]. Because of the CPS generation is high time-consumed work, the average CPU runtime for the nine circuits is more than 2000 s as shown in Fig. 11. Additionally, our scheme does not depend on the CPS, thus the CPU runtime for each circuit has met a greatly decrement with respect to the method in [16]. The experiments on the nine ITC99 and ISCAS benchmark circuits show that the CGIMT achieves a 3.97x speedup compared with the existing methods on average.

Fig. 9. Number of CGs.

Fig. 10. Area overhead evaluation.

Fig. 11. CPU runtime.

Fig. 12. Delay mitigation rate.

After obtaining the CGs using the two methods, we replace them with the fresh device to guarantee the normal lifetime for each circuit. However, the degree of optimization for each circuit could not be the same by using these two methods. In order to compare the optimization degree, we define the delay mitigation rate (DMR) as the following formation shows,

where K is the total number of the CPS in [16], ΔDi,nmitis the delay degradation of critical path Pi with no mitigation, ΔDi,mitis the delay degradation of critical path of Pi after the gate replacement. Even though our CGs number is smaller than that in [16], the mean delay mitigation rate difference for the circuits between these two methods, as Fig. 12 demonstrates, is less than 0.72%.

6. Conclusions

The CGs identification is the most important basis for circuit aging protection, while the TCLG should not be neglected in the process of CGs identification exactly as analysed above. In this paper, a time-efficient CGs identification method is proposed with considering TCLG in the circuit. As the accuracy of aging prediction for each circuit is acceptable, our method can achieve the experimental results with a 3.97x speedup and saving as much as 27.21% area overhead with the normal lifetime guaranteed, when compared with the existing methods.

[1] B. Zhao, Y. Wang, H. Z. Yang, and H. Wang, “NBTI impact on RF front end in wireless sensor networks,” Journal of Electronic Science and Technology, vol. 7, no. 4, pp. 362-369, Dec. 2009.

[2] D. K. Schroder and J. A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing,” IEEE Trans. on Applied Physics, vol. 94, pp. 1-18, Jun. 2003.

[3] W. P. Wang, S. Q. Yang, S. Bhardwaj, et al., “The impact of NBTI on the performance of combinational and sequential circuits,” in Proc. of the 44th Design Automation Conf., Washington DC, 2007, pp. 364-369.

[4] S. Bhardwaj, W. Wang, Y. Cao, et al., “Predictive modeling of the NBTI effect for reliable design,” in Proc. of 12th Custom Integrated Circuits Conf., San Jose, 2006, pp. 189-192.

[5] R. Vattikonda, W. Wang, and Y. Cao, “Modeling and minimization of PMOS NBTI effect for robust nanometer design,” in Proc. of the 43th Design Automation Conf., San Francisco, 2006, pp. 1047-1052.

[6] N. A. Conos, S. Meguerdichian, and M. Potkonjak, “Gate sizing in the presence of gate switching activity and input vector control,” in Proc. of the 21st Intl. Conf. on Very Large Scale Integration, Istanbul, 2013, pp. 138-143.

[7] S. Jin, Y. Han, L. Zhang, et al., “M-IVC: Using multiple input vector to minimize aging-induced delay,” in Proc. of the 18th Asian Test Symposium, Taichung, 2009, pp. 437-442.

[8] Y. Wang, Y. Cao, Y. Xie, et al., “Leakage power and circuit aging cooptimization by gate replacement techniques,”IEEE Trans. on Very Large Scale Integration Systems, vol. 19, pp. 615-628, Jan. 2011.

[9] L. Zhang and R. Dick, “Scheduled voltage scaling for increasing lifetime in the presence of NBTI,” in Proc. of the Asia and South Pacific Design Automation Conf., Yokohama, 2009, pp. 492-497.

[10] S. Kumar, C. Kim, and S. Sapatnekar, “Adaptive techniques for overcoming performance degradation due to aging in digital circuits,” in Proc. of the Asia and South Pacific Design Automation Conf., Yokohama, 2009, pp. 284-289.

[11] P. Krause and I. Polian, “Adaptive voltage over-scaling for resilient applications,” in Proc. of the 44th Design Automation Conf., Grenoble, 2011, pp. 944-949.

[12] Z. J. He, T. Lv, H. W. Li, et al., “An efficient algorithm for finding a universal set of testable long paths,” in Proc. of the 19th Asian Test Symposium, Shanghai, 2010, pp. 319-324.

[13] Z. J. He, T. Lv, H. W. Li, et al., “Test path selection for capturing delay failures under statistical timing model,”IEEE Trans. on Very Large Scale Integration Systems, vol. 21, pp. 1210-1219, Jul. 2013.

[14] J. J. Liou, A. Krstic, K. T. Cheng, et al., “False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation,” in Proc. of the 39th Design Automation Conf., San Francisco, 2002, pp. 566-569.

[15] I. C. Lin, C. H. Lin, and K. H. Li, “Leakage and aging optimization using transmission gate-based technique,”IEEE Trans. on Computer-Aided Design of Circuits, vol. 32, pp. 87-99, Dec. 2013.

[16] W. Wang, Z. Wang, and C. Yu, “An efficient method to identify critical gates under circuit aging,” in Proc. of the 18th Intl. Conf. on Computer-Aided Design, San Jose, 2007, pp. 735-740.

[17] W. Wang, S. Yang, and Y. Cao, “Node criticality computation for circuit timing analysis and optimization under NBTI effect,” in Proc. of the 9th Intl. Symposium on Quality Electronic Design, San Jose, 2008, pp. 763-768.

[18] D. Bild, G. Bok, and R. Dick, “Minimization of NBTI performance degradation using internal node control,” in Proc. of the 13th Design Automation Test in Europe, Munich, 2009, pp. 148-153.

[19] J. Keane, T. H. Kim, and C. H. Kim, “An on-chip NBTI sensor for measuring pMOS threshold voltage degradation,”IEEE Trans. on Very Large Scale Integration Systems, vol. 18, pp. 947-956, Oct. 2010.

[20] W. Zhao and Y. Cao, “New generation of predictive technology model for sub-45nm early design explorations,”in Proc. of the 7th Intl. Symposium on Quality Electronic Design, San Jose, 2006, pp. 2816-2823.

[21] M. Agarwal, V. Balakrishnan, and A. Bhuyan, “Optimized circuit failure prediction for aging: Practicality and promise,” in Proc. of the 19th Intl. Test Conf., Santa Clara, 2008, pp. 1-10.

[22] T. B. Chan, W. T. J. Chan, and A. B. Kahng, “Impact of adaptive voltage scaling on aging-aware signoff,” in Proc. of the 17th Design Automation Test in Europe, Munich, 2013, pp. 1683-1688.

[23] T. B. Chan, W. J. Chan, and A. B. Kahng, “On aging-aware signoff for circuits with adaptive voltage scaling,” IEEE Trans. on Circuits and Systems, vol. 61, pp. 2920-2930, Oct. 2014.

Tian-Song Yuwas born in Anhui, China in 1990. He received the B.S. degree in electronic science and technology from Hefei University of Technology (HFUT), Hefei in 2012. He currently is a postgraduate with HFUT. His research interests include circuit aging prediction and protection methods.

Hua-Guo Liangwas born in Anhui, China in 1959. He received the Ph.D. degree from the University of Stuttgart, Germany. He currently is a professor and Ph.D. supervisor in computer science at HFUT. He is the member of the Fault Tolerant Computing Technical Committee of CFF. His main research interests include Built-In Self Test (BIST), design automation of digital system, ATPG algorithm, and distributed control system.

Da-Wen Xuwas born in 1986. He received the B.S. degree in computer science from Xi’dian University, Xi’an in 2007, and the M.S. and Ph.D. degrees from the Institute of Computing Technology, Chinese Academy of Science, Beijing in 2009 and 2013, respectively. He is currently an associate professor with HFUT. His current research interests include heterogeneous computing, VLSI design and testing, and reliable system.

Lu-Sheng Wangwas born in 1981. He received the B.S. and M.S. degrees in communication engineering from Beijing University of Posts and Telecommunications, Beijing in 2004 and 2006, respectively, and the Ph.D. degree in computer and network from the Ecole Nationale Superieure des Telecommunications de Paris, Paris in 2010. He is currently a professor with HFUT. His current research interests include heterogeneous wireless & 5G cellular network and large-scale terminal/big data wireless networks.

Manuscript received November 18, 2014; revised December 30, 2014. This work was supported by the National Natural Science Foundation of China under Grant No. 61274036, No. 61371025, No. 61204027, and No. 61474036.

T.-S. Yu is with the School of Electronic Sicence and Applied Physics, Hefei University of Technology, Hefei 230009, China (Corresponding author e-mail: yutian song19@163.com).

H.-G. Liang, D.-W. Xu, and L.-S. Wang are with the School of Electronic Sicence and Applied Physics, Hefei University of Technology, Hefei 230009, China.

Digital Object Identifier: 10.11989/JEST.1674-862X.411181