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    Symbolic Macromodeling for Statistical Simulation of Operational Amplifiers

    2013-11-26 10:47:56LanLanDongGuoYongShiandJianDongCheng

    Lan-Lan Dong, Guo-Yong Shi, and Jian-Dong Cheng

    1.Introduction

    The art of operational amplifier (op-amp) macromodeling has been a constantly studied research subject since the beginning of monolithic integrated circuit (IC)op-amps[1].The two-pole macromodel shown in Fig.1 has been widely used in the literature for small-signal analysis of two-stage amplifiers[2].Some early works[3],[4]adopted the two-pole model by incorporating nonlinear devices(transistors or diodes) in order to characterize the large-signal transient behaviors.Obviously, these models take different forms in the frequency and time domains.

    In 1982 Chuang[5]proposed a second-order behavioral model (Fig.2) for behavior analysis of slewing and settling of two-stage op-amps.The model consists of a current limiter in the feedforward path which reflects the current limiting effect by some transistor in the op-amp.The block denoted by H(s) is the two-pole model shown in Fig.1.

    For an instant step input, the voltage input to the current limiter is large and the current limiter in Fig.2 is in saturation when the output starts to slew.During this period the feedback loop is virtually not in effect.As the output waveform settles to the vicinity of the final value, the current limiter enters the linear operation and the feedback loop becomes effective, and the settling behavior is governed by a linear system.

    Several works have attempted to improve Chuang’s model from a variety of aspects, such as Lin and Nevin[6]for smooth transition from slewing to settling, Wang and Harjani[7]for improved slew rate formula when more advanced technology is used, and Yavari et al.[8]for the case when the op-amp output stage is limited to low-current operation.The different slew rate formulas proposed only apply to circuits with the assumed working conditions but lack the generality for use in design automation tools.

    The recent work in [9]developed a unified formulation for slew and settling analysis by adapting Chuang’s two-pole model into a symbolic setting.However, in that work the second-order linear block H(s) which is constructed by extracting approximate poles does not have the circuit-form representation shown in Fig.1.

    Fig.1.Two-pole macromodel for a two-stage op-amp.

    Fig.2.Chuang’s behavioral model for transient analysis[5].

    This paper is a continuation of the work in [9]by proposing a new symbolic construction of the behavioral model which takes the behavioral circuit-form shown in Fig.1.The advantage of maintaining a macromodel in circuit form is that it can be extended easily to multiple-stage op-amp designs because the building blocks used in Fig.1 are standard.By inserting such a symbolic model in the Chuang’s behavioral configuration shown in Fig.2, both small-signal and large-signal op-amp performance characteristics can be evaluated by behavioral simulation.Moreover, the proposed macromodel can be used for fast Monte Carlo characterization of the op-amp slew and settling behavior, which was not studied in [9].Process variation is currently one of the major issues that affect the yield and product quality of nanometer integrated circuits.Statistical verification of analog ICs has been the subject of some recent publications, such as techniques on Monte Carlo sampling[10]and symbolic methods to predict the circuit response variations in the frequency and time domains[11]-[13].The proposed symbolic macromodeling method is developed in Section 2.Experimental validation of the accuracy and speed of the proposed model for statistical simulation is presented in Section 3.This paper is concluded in Section 4.

    2.Symbolic Modeling Method

    2.1 Two-Port Admittance Model

    A multi-stage op-amp circuit is composed of several two-port stages.Each stage can be described by the following 2×2 small-signal admittance equation

    where the four admittance parameters correspond to those shown in Fig.3 (a).The input conductance g11is usually very small (or impedance very high) for MOS op-amps;hence, the input port can be assumed open.In this work, we use the simplified two-port model shown in Fig.3 (b).Note that the two-stage macromodel shown in Fig.1 consists of two stages of such simplified two-port models.

    Fig.3.Two-port circuit models: (a) two-port circuit model and (b)simplified two-port circuit model.

    2.2 Symbolic Model Generation

    Assume that a circuit block with one input and one output has a rational transfer function in the following s-expanded form:

    With a symbolic tool, this function can be derived in the form that all the coefficients bj’s and ak’s in (2) are analytical functions of the small-signal parameters of the corresponding circuit block[14],[15].When the circuit parameters change, the values of these coefficients can be computed accordingly without carrying out a new construction.

    Suppose that H(s) is in admittance form.Let the Taylor expansion of H(s) at s = 0 be

    where the coefficients mkare called moments[16].

    The two admittance parameters given in the two-port schematic in Fig.3 (b) have the following forms

    where gmis a transconductance, R is a resistive load, and C is a capacitive load.These two expressions are already in the s-expanded forms of the 0th and 1st orders.The coefficients can be determined by matching the coefficients to (3).

    Assume that an op-amp is of finite dc-gain, i.e., a0≠ 0.Then by moment-matching (2) and (3), we have

    Since the coefficients a0, a1, b0, and b1are symbolic functions of the circuit small-signal parameters, so are the moments m0and m1.Consequently, the parameters gm1, gm2,R1, R2, C1, and C2appearing in the two-pole macromodel in Fig.1 can be derived as analytical functions of the small-signal parameters of the original op-amp circuit.

    We emphasize again that such symbolic construction is carried out only once for any given circuit.The constructed behavioral model can be used repeatedly for statistical computation provided that the small-signal parameter values are updated when necessary.The proposed macromodeling steps are summarized below.

    Step 1: Given a multi-stage op-amp, use the final value of the step input for simulating the dc operating point and generating the small-signal circuit parameter values (it is usually an HSPICE simulation.)

    Fig.4.Two-stage behavioral model containing a current limiter G.

    Step 2: Partition the circuit into several cascaded two-port blocks.Remove the biasing and feedback parts of circuit if necessary.

    Step 3: Use a symbolic ac analysis tool to obtain the port transadmittances of each stage.Use (5) to determine the moments m0and m1.Use (4) to determine the macromodel parameters.

    Step 4: Place back the feedback compensation elements(e.g.the capacitor CCand the nulling resistor RCif needed)in the macromodel.

    2.4 Use of the Macromodel

    Both the current limiter and the second-order H(s)model in Fig.2 (i.e., the Chuang’s behavioral model) can be described in standard HSPICE netlist.The current limiter can be described by a G element with saturation[17]in HSPICE:

    Replacing the transconductance gm1in the two-pole model (Fig.1) by the current limiter G just defined, we get the behavioral model shown in Fig.4, where the current limiter is embedded in the two-stage model H(s).

    3.Simulation Results

    The simulation results in both frequency domain and time domain are presented in this section.The TSMC 0.18 μm technology was used for simulation.Two op-amp circuits were used to validate the accuracy and efficiency of the proposed modeling method.

    Circuit A in Fig.5 is a simple two-stage op-amp and Circuit B in Fig.6 is a rail-to-rail folded-cascode op-amp.The robustness of the proposed model is illustrated by changing the circuit working conditions, e.g.different supply voltages for the two circuits.In the transient simulations, the op-amps are connected as a voltage follower shown in Fig.7.

    Fig.5.Circuit A: a simple two-stage operational amplifier.

    Fig.6.Circuit B: a rail-to-rail folded-cascode amplifier.

    Fig.7.Voltage follower.

    Fig.8.Comparison of the frequency responses for Circuit B.

    Fig.9.Comparison of the transient responses of Circuit B.

    Fig.8 shows the frequency responses of Circuit B by using the macromodel and HSPICE; the results agree very well.Fig.9 shows the transient step responses of Circuit B by using the two macromodels (the proposed symbolic model and Chuang’s non-symbolic model) and HSPICE.Except for the slight deviation by using Chuang’s non-symbolic model, the waveform produced by the symbolic macromodel agrees very well with that of HSPICE.Similar results were observed for Circuit A.

    As pointed out by Yavari et al.in [8], the classical slew rate formula (also used in Chuang’s model) was not accurate for low-current operation.Hence, it is of interest to examine whether the proposed behavioral model can predict accurate slew rates in different circuit operating conditions.Fig.10 shows a comparison of the slew rates of Circuit A measured by the three different models.The supply current was adjusted in simulation by adjusting the width of the transistor M7 from 38 μm to 60 μm.The curves show that our symbolic macromodel estimates the slew rate as accurate as the HSPICE transistor-level simulation results for different supply currents, whereas Chuang’s model failed to predict the correct slew rates when the current level is low.This test testifies that the proposed symbolic behavioral model is more robust to varying operating conditions.

    The statistical simulation results were tested for the transient response of Circuit B by varying the compensation capacitor CC.In the experiment, the values of CCwere sampled by a normal distribution with the mean μ=4 pF and the standard variance δ=1/3 pF, and with the maximum absolute variation truncated at 1 pF (i.e., 3δ = 1 pF by the HSPICE agauss command).

    Fig.11 and Fig.12 show the Monte Carlo slew rate and settling time results of 10000 samples by using the proposed macromodel and HSPICE.The accurate agreement is further justified by the scatter plots shown in Fig.13.It can be seen that the statistical variation of the feedback capacitive compensation can be very accurately characterized by the proposed method.Finally, Fig.14 shows that using the macromodel for statistical simulation is more advantageous in speed than running repeated HSPICE simulations.

    Fig.10.Comparison of the slew rates of Circuit A computed by the three methods with respect to the size of M7.

    Fig.11.Comparison of slew rate distribution for Circuit B.

    Fig.12.Comparison of settling time distribution for Circuit B.

    Fig.13.Scatter plots of the data shown in Fig.11 and Fig.12: (a)slew rate and (b) settling time.

    Fig.14.Monte Carlo runtime comparison for Circuit B.

    4.Conclusion

    A symbolic behavioral modeling method has been proposed for general multiple-stage operational amplifiers.The feature of symbolic model parameters can facilitate the simulation of varying circuit operating conditions, which is advantageous for statistical analog circuit verification.The experimental results have specifically demonstrated that the proposed model can be used efficiently to predict the large-signal behavior of op-amps in the time domain, which has hardly been addressed in the open literature.

    Acknowledgment

    The first author wishes to thank Tingting Tao and Jinbo Li for many valuable discussions.

    [1]J.Solomon, “The monolithic op amp: a tutorial study,” ⅠEEE Journal Solid-State Circuits, vol.9, no.6, pp.314-332,1974.

    [2]P.R.Gray and R.G.Meyer, Analysis and Design of AnalogⅠntegrated Circuits, 2nd ed.New York: John Wiley & Sons,Inc., 1990.

    [3]G.Boyle, D.Pederson, B.Cohn, and J.Solomon,“Macromodeling of integrated circuit operational amplifiers,” ⅠEEE Journal of Solid-State Circuits, vol.9, no.6, pp.353-364, Dec.1974.

    [4]C.Turchetti and G.Masetti, “A macromodel for integrated all-MOS operational amplifiers,” ⅠEEE Journal of Solid-State Circuits, vol.18, no.4, pp.389-394, 1983.

    [5]C.T.Chuang, “Analysis of the settling behavior of an operational amplifier,” ⅠEEE Journal of Solid-State Circuits,vol.17, no.1, pp.74-80, Feb.1982.

    [6]J.C.Lin and J.H.Nevin, “A modified time-domain model for nonlinear analysis of an operational amplifier,” ⅠEEE Journal of Solid-State Circuits, vol.21, no.3, pp.478-487,1986.

    [7]F.Wang and R.Harjani, “An improved model for the slewing behavior of opamps,” ⅠEEE Trans.on Circuits and Systems ⅠⅠ: Analog and Digital Signal Processing, vol.42,no.10, pp.679-681, Oct.1995.

    [8]M.Yavari, N.Maghari, and O.Shoaei, “An accurate analysis of slew rate for two-stage CMOS opamps,” ⅠEEE Trans.on Circuits and Systems ⅠⅠ: Express Briefs, vol.52,no.3, pp.164-167, 2005.

    [9]H.Zhang and G.Shi, “Symbolic behavioral modeling for slew and settling analysis of operational amplifiers,” in Proc.of ⅠEEE the 54th Midwest Symposium on Circuits and Systems, Seoul, 2011, pp.1-4.

    [10]A.Singhee and R.A.Rutenbar, “Why quasi-Monte Carlo is better than Monte Carlo or Latin hypercube sampling for statistical circuit analysis,” ⅠEEE Trans.on Computer-Aided Design of Circuits and Systems, vol.29, no.11, pp.1763-1776, Nov.2010.

    [11]G.Shi and X.Meng, “Variational analog integrated circuit design by symbolic sensitivity analysis,” in Proc.of Ⅰnt.Symposium on Circuits and Systems, Taipei, 2009, pp.3002-3005.

    [12]Z.Hao, S.X.D.Tan, R.Shen, and G.Shi, “Performance bound analysis of analog circuits considering process variations,” in Proc.of ⅠEEE/ACM Design Automation Conf.,San Diego, 2011, pp.310-315.

    [13]X.Liu, S.X.D.Tan, Z.Hao, and G.Shi, “Time-domain performance bound analysis of analog circuits considering process variations,” in Proc.of Asia South-Pacific Design Automation Conf., Sydney, 2012, pp.535-540.

    [14]C.J.R.Shi and X.D.Tan, “Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design,” ⅠEEE Trans.on Computer-Aided Design of Ⅰntegrated Circuits and Systems, vol.20, no.7, pp.813-827, 2001.

    [15]G.Shi, W.Chen, and C.J.R.Shi, “A graph reduction approach to symbolic circuit analysis,” in Proc.of Asia South-Pacific Design Automation Conf., Yokohama, 2007,pp.197-202.

    [16]L.T.Pillage and R.A.Rohrer, “Asymptotic waveform evaluation for timing analysis,” ⅠEEE Trans.on Computer-Aided Design of Ⅰntegrated Circuits and Systems,vol.9, no.4, pp.352-366, April 1990.

    [17]HSPⅠCE Simulation and Analysis User Guide, Synopsys,Inc., Mountain View, CA, March 2006, version Y-2006.03.

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