Single-event Burnout Effect on Radiation-hardened High-voltage NMOS

LI Yanfei, SUN Jialin, WANG Lei, WU Jianwei, HONG Genshen, HE Qi

(The 58th Research Institute of China Electronics Technology Group Corporation, Wuxi 214035, China)

Abstract: Single-event gate rupture (SEGR) and single-event burnout (SEB) are the significant radiation threats from heavy ions due to the high applied gate voltage. The single-event burnout effect on radiation-hardened high-voltage SOI NMOS was reported. The hardened layout and p-type ion implantation process were developed to enhance the hardened structure against SEB effect, and the critical device parameters were designed and chosen according to electrical specifications. The SEB effect was studied in detail based on both simulated and experimental results. The experiment data demonstrate that the radiation-hardened device achieves a high drain voltage of 24 V under single-event irradiation with a linear energy transfer (LET) threshold value of 83.5 MeV·cm2/mg.

Key words：high-voltage SOI NMOS; radiation-hardened; single-event burnout; linear energy transfer

1 Introduction

Compared with low-voltage integrated circuit, high-voltage MOSFET device is more prone to single-event effect due to higher operating voltage and larger inductive and capacitive loads[1-2]. In the gate driver, high-voltage MOSFET is used to provide a rail-to-rail output. For high-voltage device, the most concerned single-event effects are single-event burnout (SEB)[3-12]and single-event gate rupture (SEGR)[13-16]. Destructive SEB effect can be induced by the strike of a heavy ion through a MOSFET when it is biased in the off-state. When the ion is incident into the MOSFET device, a large number of electron-hole pairs are generated, and the transient current is formed under the dual effects of drift and diffusion. When the voltage drop of the transient current on the well resistance increases to a certain value, the parasitic bipolar transistor inherent in the MOSFET structure is turned on, and the regenerative feedback causes catastrophic device failure.

In recent years, significant radiation-hardened structures for the development of MOSFET have been achieved, and the optimum balance between the drain voltage and resistivity that meets the requirement of the specific application has been realized. Avalanche-generated holes returning from the base-collector region are the key to sustaining a regenerative feedback process that may lead to a state with simultaneous high current and high-voltage. Numerous studies have been implemented investing SEB in high-voltage MOSFET. In this paper, a radiation-hardened high-voltage SOI NMOS is designed by TCAD simulation. The p-type ion implantation process and layout optimization are introduced to provide remarkable improvements in SEB threshold voltage for the radiation-hardened device.

2 Experimental detail

2.1 Simulation experiment

The novel NMOS device has been fabricated by the radiation-hardened high-voltage SOI CMOS process, which is used in the output driver section of gate driver ICs. With the typical supply voltage of 15 V, the output NMOS device has maximum gate-source voltage (Vgs) of 20 V and drain-source voltage (Vds) of 20 V.Fig.1a shows the schematic cross-sectional view of radiation-hardened structures. The p-type buried (P-buried) layers are introduced underneath the top silicon layer and under heavily doping source, which creates an optimum balance between the breakdown voltage and resistivity of p-type well (P-well). Due to the high doping concentration of P-buried layers, the parasitic bipolar transistor requires higher radiation-induced current to turn on compared with the conventional structure. The lengths of channel region and drift region (NHV) are namedLgandLn, respectively, which play a major influence on the SEB effect for the device. 3D structures of radiation-hardened and conventional NMOS devices are shown in Fig.1b and Fig.1c, respectively. Compared with the conventional structure, the hardened waffle layout of the proposed NMOS is optimized by short source-body structure, which can rapidly accelerate radiation-induced current transmission to prevent the actuation of parasitic bipolar transistor. Table 1 presents the value of main structure and process parameter. The radiation-hardened gate oxide of 80 nm is developed for SEGR effect which is caused by the combination of the applied electric field and the energy deposited by the ion. The thickness of the top silicon (TSi) and buried oxide layer (Tbox) are 4 μm and 3 μm, respectively. Based on the p-type ion implantation process and epitaxial process, the P-buried layers are implemented by the implanted dose of 1×1014cm-2.

Fig.1 Schematic cross-sectional view of radiation-hardened NMOS (a), 3D structures of radiation-hardened NMOS (b) and conventional NMOS (c)

Table 1 Value of main parameter for proposed NMOS

2.2 SEB experiment

The SEB experiment was performed at Heavy Ion Research Facility in Lanzhou (HIRFL) accelerator in Institute of Modern Physics, Chinese Academy of Sciences. The181Ta ion was used to characterize and verify the SEB hardness of the conventional and proposed NMOS structures. All devices were mounted in 16-pin ceramic dual-in-line packages, and the lid was no installed to allow the ion beam to directly hit the die surface. The test samples were loaded onto the test boards and placed into the beam line. When it was ready, the beam shutter was removed and began the irradiation of the test sample. Quiescent bias current was monitored with Keithley 2636B source meters and used to predict device acceptance. Under the irradiation, the devices were biased to stepped drain voltage. Once the desired fluence was achieved the beam was automatically shuttered and the bias was removed.

Table 2 presents the beam parameter for the181Ta ion utilized. The energy of Ta ion was 2006.4 MeV. The fluence and flux specified for this test were 1×107cm-2and 1×104cm-2·s-1, respectively. The heavy ion beam area was 2.3 cm×2.3 cm. The angle of incidence was set to 90° (normal to the die surface) with LET=83.5 MeV·cm2/mg. When the leakage current rapidly increased by 1 μA, the destructive damage of devices occurred. The previous stepped drain voltage was treated as the SEB threshold voltage. All the irradiations were performed at room temperature, as well as the electrical measurements.

Table 2 Ion beam parameter

3 Result and analysis

3.1 Simulation result and analysis

When a heavy ion penetrates a device structure, it loses energy and creates a trail of electron-hole pairs which may cause a large enough current to switch the logic state of a device. To investigate the SEB behavior, a series of transient simulations were conducted by TCAD. The gate electrode is shorted to the source to ensure the SOI NMOS devices in the off-state. Simultaneously, the LET value and drain voltage applied on the device were increased gradually to identify the maximum critical value without SEB effects, which defined as the critical LET value and the SEB threshold voltage.

Fig.2 Simulated drain current and lattice temperature for conventional and hardened NMOS devices

Fig.2 shows the simulated drain current and lattice temperature for conventional and hardened NMOS devices atVds=20 V. When the energetic heavy ion of LET=100 MeV·cm2/mg travels into the device, huge transient current is produced in the SOI NMOS. The parasitic bipolar transistor inherited can be triggered if the transient current passes the sensitive area. For the conventional structure, the drain current maintains constant of 6.44 mA and lattice temperature increases continually up to 1600 K during the transient process, which reveals that the SEB happens. However, the hardened technologies are used to keep the transient current away from the P-well region below the heavily doping source, and the hardened structure shows no SEB. The maximum drain current of 1.76 mA and lattice temperature of 337 K are achieved, and then both are restored to their former state. Therefore, the hardened NMOS presents a superior SEB survivability.

Fig.3 shows the simulated SEB threshold voltage as a function of LET value. AtLg=Ln=4 μm, the conventional devices perform poor SEB threshold voltage of 15 V at LET=100 MeV·cm2/mg. With the sameLgandLn, the SEB threshold voltage above 25 V is observed with the LET value ranging from 30 MeV·cm2/mg to 100 MeV·cm2/mg for the hardened devices. As scaling down ofLgandLn, the resistance to SEB attenuates. WhenLgdecreases to 3 μm, the SEB threshold voltage of 21 V is obtained by the hardened structure with the LET value of 100 MeV·cm2/mg, because of the shorter base width of the parasitic bipolar transistor. The collector resistance of parasitic bipolar transistor reduces and collector collection efficiency increases with lowerLn. As shown in Fig.3, the SEB threshold voltage is more sensitive to the channel length. On the basis of these simulation data, the conventional and hardened devices have been manufactured atLg=Ln=4 μm.

Fig.3 Simulated SEB threshold voltage as a function of LET value

3.2 Device characteristic and analysis

Based on the radiation-hardened high-voltage SOI CMOS process, the conventional and hardened SOI NMOS devices were fabricated with the same area of 850 μm×450 μm.Fig.4 shows output characteristic curves of the conventional and hardened SOI NMOS with differentVgsof 5 V, 10 V, and 15 V. AtVgs=Vds=15 V, the conventional structure achieves a high drain current of 2.15 A. While the hardened NMOS exhibits a slight lower output current of 2.1 A, which is decreased only by 2.32%. The current curve of hardened NMOS almost coincides with the curve of conventional NMOS fitted by using actual measurement data. It indicates that the output characteristics of the devices will not be deteriorated by the radiation-hardened method. As a result, the hardened NMOS has roughly the same current capability as the conventional NMOS.

Fig.4 Output characteristic curves of conventional and hardened SOI NMOS devices

3.3 SEB result and analysis

Each irradiation was carried out to a fluence of 1×107cm-2. The leakage current was monitored to look for indications of device damage, and then the irradiated devices were returned for subsequent electrical testing.Fig.5 shows the leakage current as a function of Ta ion radiation fluence with stepped drain voltage for conventional and radiation-hardened high-voltage SOI NMOS devices. For the two structures, the leakage current increases slowly as the ion fluence raises. With a drain voltage of up to 18 V, the leakage current for the conventional device abruptly increases by four orders of magnitude, which indicates that the device is damaged. With drain voltage from 14 V to 24 V, the leakage current increases gradually due to the higher electrical field applied at the drain region. The leakage current is with a mean value of 100 pA atVds=24 V for the radiation-hardened device, which means that there is no permanent damage sustained by the parts for any of the SEB testing completed.

Fig.5 Leakage current as a function of ion fluence with stepped drain voltage

Fig.6a shows the gate leakage current and breakdown characteristics after the Ta ion exposure experiments. The two structures have nearly breakdown voltage up to 75 V as shown in the curves. At gate voltage of 20 V, the conventional and hardened devices achieve gate current of 9.65 pA and 1.0 pA, respectively. It should be noted that the SEGR phenomenon didn’t happen in both the conventional device and hardened device owing to 80 nm gate oxide.Fig.6b shows the breakdown characteristic before and after irradiation. With the lightly doping NHV region, the hardened and conventional devices have high breakdown voltage of 45.5 V and 47 V before irradiation, respectively. After heavy ion exposure, the hardened device achieves drain current of 183 pA, which is approximately equal to the monitored current during irradiation shown in Fig.5. The new body contact structure and P-buried layers introduced in P-well region are used to discharge the radiation-induced charges and leakage current before they arrive the sensitive area of the parasitic bipolar transistor. However, the drain current quickly rises to 1 μA atVds=13 V for the conventional device, which suggests the occurring of SEB behavior. Thus, the radiation-hardened device demonstrates a superior SEB performance.

Fig.6 Gate current after ion irradiation (a) and drain current before and after heavy ion irradiation (b)

4 Conclusion

In this work, the proposed high-voltage NMOS has been designed and fabricated with the p-type buried layer and optimized waffle layout based on the radiation-hardened high-voltage SOI CMOS process. According to the TCAD simulation, the channel length has more influence on the SEB performance. The experimental data show that the SEB threshold voltage for hardened devices is found of 24 V at LET=83.5 MeV·cm2/mg, which is increased by 50% compared with conventional devices. It is suggested that the radiation-hardened technique yields significant improvement in the resistance capability to SEB effect.