Comprehensive Understanding of Hot Carrier Effect of PDSOI NMOS Devices Fabricated on Modified Wafer

LIU Chunmei, YANG Xu, ZHU Huilong, HU Zhiyuan, BI Dawei,*, ZHANG Zhengxuan

(1.State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China; 2.University of the Chinese Academy of Sciences, Beijing 100049, China; 3.Hua Tian Technology (Kunshan) Electronics Co., Ltd., Kunshan 215300, China)

Abstract: The hot carrier induced degradation of PDSOI NMOS devices fabricated on wafers modified by silicon ions implantation was elaborately studied in this paper in comparison with conventional devices. Theoretical analysis and TCAD simulation results show that the electron traps in the buried oxide layer induced by silicon ions implantation can capture the injected electrons and affect the intensity of impact ionization and hot carriers injection by altering the electric field. Meantime, the effect varies in different stress conditions. When hot carrier stress is applied to the modified device, there is a more significant interaction between the front and back gates of the modified device. The effect of total dose irradiation on the hot carrier degradation was also explored. The radiation enhanced hot carrier degradation also occurs in the modified devices and high-temperature annealing can only partially eliminate this effect.

Key words：hot carrier effect; total dose irradiation; radiation hardening; PDSOI NMOS; modified device

1 Introduction

SOI devices have good resistance to single event effect and transient dose rate effect due to their unique buried oxide (BOX) layer, but they are also more vulnerable to total dose effect[1-3]. Fortunately, lots of techniques have been proposed to improve the ability against total dose effect for SOI devices. And the injection of silicon ions into the BOX layer has been proved to be an effective method in many papers[4-6]. Although silicon ions implantation does have a positive effect on the total dose resistance of SOI devices, the silicon nanoclusters in the BOX can lead to abnormal hot carrier degradation in PMOS devices[7]. On the other hand, in the space environment, devices face the threat of radiation environment as well as the threat of reliability such as the hot carrier effect. The research on the combined effects of irradiation and hot carriers injection has been carried out by many researchers[8-11]. Acovic et al. have studied the reduced hot-carrier reliability degradation of X-ray irradiated 0.25 μm CMOS[8]. Jiangwei Cui et al. have studied the impact of TID radiation on hot carrier effect in PDSOI NMOS and PMOS[10-11]. These studies are mostly concentrated on radiation unhardened devices, and the research on radiation-hardened devices is limited. In this paper, we mainly focus on the hot carrier induced degradation of PDSOI NMOS devices fabricated on the modified wafers, comparing with normal commercial SOI devices, and try to explore the effect of total dose irradiation on the hot carrier degradation of the modified devices.

Fig.1 Layout and cross section of H-gate device used in our experiment

2 Material and method

The control wafers used in our experiment were from SOITEC Corporation’s 200 mm diameter UNIBOND wafers with a 100 nm Top-Si film and a 145 nm BOX, and the modified wafers were fabricated by implanting silicon ions into the BOX layer. The PDSOI NMOS devices withW/L=10 μm/0.35 μm were fabricated by 130 nm PDSOI CMOS technology. The H-gate is used for body contact, as shown in Fig.1. All devices were 24-pin DIP ceramic packaged. The radiation source was60Co-γ ray, and the dose rate was 200 rad(Si)/s. The devices were irradiated up to 300 krad(Si) under ON bias condition (Vfg=3.63 V,Vd=Vs=Vb=Vbg=0). The hot carrier stress and measurement processes were completed automatically on a Keithley 4200 semiconductor parameter analyzer. Both the irradiation and stress process were carried at 25 ℃. When stress time accumulated to 10, 30, 100, 300, 1000, and 3000 s, the stress was temporarily interrupted for measurement. The threshold voltage and maximum transconductance in the front and back gate transistor were measured by theId-Vgcurves. There are three kinds of front gate stress bias and two kinds of back gate stress in our experiment.

Front gate stress:

1) LowVfg,Vfg=0.7 V,Vd=4.6 V, which leads to the maximum body current.

2) MiddleVfg,Vfg=2.3 V,Vd=4.6 V.

3) HighVfg,Vfg=Vd=4.6 V, which leads to the maximum gate current.

And back gate stress:

1) LowVbg,Vbg=13 V,Vd=4.6 V, which leads to the maximum body current.

2) HighVbg,Vbg=30 V,Vd=4.6 V, which leads to the maximum back gate current.

It should be noted that the fabricated process of these two devices is identical except that the wafers used are different. So the differences in electrical parameters such as threshold voltage, saturation current, and max-imum linear transconductance between them can be ignored before experiment.

3 Result and discussion

3.1 Front gate HCI stress

Fig.2 Time dependence of degradation of Vt,fg and Gm,fg for devices suffered front gate HCI stress

For NMOS, interface states are negatively charged during the measurement in strong inversion, resulting in the increase of threshold voltage. Furthermore, as an additional scattering center, they reduce the carrier mobility and lead to the decrease of transconductance. The time exponentn≈0.5 as long as ΔNitis negligible compared to the initial density of Si—H bonds (n0)[12]. At larger degradation or longer stress times, saturation effect occurs with a decrease ofn0, causing a smaller time exponentn. And this is whyn≈0.15 for δGmof our device. Meantime, due to the parasitic bipolar transistor effect of PDSOI devices, both hot holes and hot electrons injection occur at the drain side of the front channel, resulting in trapped changes[13]in the gate oxide. And the gate injection current can be described as[14-15]:

Jinj∝exp(-φb(Eox)/qλEm)P(Eox)

(1)

whereφbis the barrier energy of electron/hole,Eoxis the vertical electric field at the gate oxide andP(Eox) is the possibility that a hot electron/hole can travels to the Si—SiO2interface and then reach the barrier peak in the oxide without suffering any collision which is exponentially related toEox.

At the early stage of lowVfgstress, the interface states and electron injection contribute to the increase ofVt,fgthough the hole injection occurs at the same time. With the process of stress, the potential barrier height of electrons (φb) is increased due to the electrons trapping at the interface[16]and the injection of electrons into the gate oxide is also influenced by it[17]. Meanwhile, the injected holes accumulated at the drain terminal shorten the effective channel length and cause the channels located near the drain terminal to become the pinch-off region, so that influence of interface states onVt,fgis masked. The degradation ofVt,fgbecomes dominated by the hole injection, soVt,fgdecreases with stress time. For the modified devices, silicon ions implantation forms a large number of silicon nanoclusters in the BOX, which can act as deep level electron traps[18]. Although the devices used in our experiments are partially depleted SOI devices when the hot carrier stress is applied to the front gate, the degradation of the hot carriers also occurs at the back gate due to the thin top silicon. This can be verified by the great increase ofVt,bgas shown in Fig.3 (Vd=4.6 V, the solid line represents control group, and the dotted line represents modified group). On the other hand, the charges in the BOX can change the electric field distribution in the front gate. To verify this, we used Sentaurus TCAD software to simulate the electric field distribution for modified devices by placing negative charges with a surface density of 1×1012cm-2on the upper part of the BOX layer of the device. Then we extracted the lateral and vertical electric field along the front channel of devices under different HCI stress as shown in Fig.4 (Vd=4.6 V, the solid line represents control group, and the dotted line represents modified group). The device channel is located in the range of coordinates (-0.175, 0.175) and the positive vertical electric field points from the top interface of the Top-Si to the bottom interface on Fig.4. As we can see from the insert chart on Fig.4a, a large number of electrons in the BOX of modified devices enhance the maximum lateral electric field (Em) at the drain terminal near the front channel, indicating the larger intense of impact ionization. Thus the modified devices show more severe degradation ofGm,fgon Fig.2b. In the meantime, as shown in Fig.4b, these electrons also enhance the forward electric field, which enlarges the injection of electrons and weakens the injection of holes for front gate. As a result, the electrons injection and interface states dominate the degradation of the front channel for the modified device during the whole stress time. Therefore, theVt,fgof it keeps increase with the stress time in a power relationship.

Fig.3 Time dependence of degradation of Vt,bg and Gm,bg for devices suffered front gate HCI stress

For the case ofVfg=2.3 V, the degradation of the front gate is dominated by impact ionization and electrons injection for both con-trol and modified devices. Because theEmdecreases compared with the lowVfgstress, i.e., the impact ionization strength weakens, the degradation ofGm,fgis more lightly. Meantime, due to the smaller initial degradation, the saturation effect is weaker. So thenof δGm,fgincreases to about 0.25. Because of the enhancement of the impact ionization at the front channel caused by the electrons trapped in the BOX, the modified devices show worse degradation ofGm,fgthan the control devices.

For the case ofVfg=4.6 V, electron injection dominates the hot carrier degradation of the front gate. And the degradation ofGm,fgis modest, implying the most delicate impact ionization. The time exponentnof δGm,fgincreases to about 0.3. Meantime, the electrons injected into the BOX at high gate voltage stress is meager, so there is no significant difference between the modified and control devices.

When the hot carrier stress was applied at the front gate, the hot carrier degradation also occurs at the drain terminal of the back channel, as shown in Fig.3. For the control device, the degradation ofVt,bgis similar to that of the front gate. At lowVfgstress, theVt,bgfor control device increases firstly and then decrease with the stress time due to the initial generation of interface traps followed by hole injection. However, for the case ofVfg=2.3 V, the interface traps and electron injection contributed to the hot carrier degradation, and theVt,bgincrease with the stress time in a logarithmic law (Δ=Blnt-C) relationship rather than a power-law relationship as the front channel. In the logarithmic-law relationship,Bis the slope in a semi-log plot andC, same as the role ofAin the power low relationship, indicates the magnitude of degradation at the initial stage. When theVfg=4.6 V, the lateral and vertical electric field at the top interface of the BOX are both weakest, as shown in Fig.5 (Vd=4.6 V, the solid line represents control group, and the dotted line represents modified group), leading to limited interface states and injected electrons, thus the degradation ofVt,bgis light. As for the modified devices, however, theVt,bgfor lowVfgand middleVfgcases increase sharply with the stress time in a logarithmic-law relationship, because the electron traps formed by silicon nanoclusters can easily capture the electrons injected into the BOX during the stress. In addition, whenVfg=4.6 V, the injected electrons is limited due to the reduced vertical electric field, thus the positive shift ofVt,bgfor the modified device is comparable to that of the control device.

Fig.3 Simulated lateral and vertical electric fields along front channel at different Vfg

On the other hand, there are interface traps generated in the back channel in both the control and modified devices, which leads to a reduction inGm,fgwith a logarithmic relationship as shown in Fig.3b. What’s more, theBvalue decreases as theVfgincrease, which is contributed to that the maximum lateral electric field at the back channel decreases as theVfgincrease, seen from Fig.5a. Although the captured electrons in the BOX enhanced theEmalong the back channel, they also drive the major carriers (electrons) in the back channel away from the back gate, which mitigates the effects of coulomb scattering. Therefore, the modified devices exhibited weaker degradation ofGm,fg. At highVfg, fewer electrons are trapped, so this weakening effect is negligible.

3.2 Back gate HCI stress

Fig.6 shows the time dependence of the degradation ofVt,bgandGm,fgof the modified and control devices which suffered the back gate HCI stress (Vd=4.6 V, the solid line represents control group, and the dotted line represents modified group). The degradation ofVt,bgandGm,fgwith stress time match the logarithmic-law relationship (Δ=Blnt-C). For control devices, electron injection and interface states induced by impact ionization lead to the significant forward shift of threshold voltage for both cases. As shown in Fig.7, the maximum lateral electric field of the back channel in the case ofVbg=13 V is larger than that ofVbg=30 V, but the negative vertical electric field is smaller. Thus, the larger impact ionization rate induced by the larger lateral electric field in the case ofVbg=13 V contributes to the more obvious degradation ofGm,fg. The more injected electrons caused by the larger vertical electric field in the case ofVbg=30 V results in more significant threshold voltage increase. For modified devices, in the early stage of stress, the electron traps in the BOX captured extensive electrons rapidly, which leads to the significant increase in the threshold voltage. These large numbers of electrons change the electric field distribution on the back channel during the stress, as shown in Fig.7 (Vd=4.6 V, the solid line represents control group, and the dotted line represents modified group). On the one hand, similar to the situation ofVfgstress, although the electrons in the BOX increase theEmon the back channel, they drive the electrons away from the interface, reducing the surface scattering and improving the electron mobility. So theGm,fgof the modified devices increases sharply when the stress was just carried for 10 s and then gradually decrease with the stress time. What’s more, the reduced vertical electric field obstructs the subsequent electron injection during the stress. In addition, most of the deep electron traps was occupied in the early stage of the stress, meaning that the unoccupied electron traps reduced sharply. Thus the degradation rate (theBvalue) ofVt,bgfor modified devices is not much greater than that for the control devices.

Fig.5 Simulated lateral and vertical electric fields along back channel at different Vfg

Fig.6 Time dependence of degradation of Vt,bg and Gm,fg for devices suffered back gate HCI stress

Fig.7 Simulated lateral and vertical electric fields along back channel at different Vbg

Fig.8 indicates the front gate also suffered hot carrier induced degradation during the back gate HCI stress (Vd=4.6 V, the solid line represents control group, and the dotted line represents modified group). And the degradation is contributed by the impact ionization and holes rather than electrons injection. For the case ofVbg=13 V, the degradation is dominated by the interface states generation which induced the decrease of theGm,fgand increase ofVt,fg. Similar to the previous case of front gate HCI stress, when there are enough holes accumulated at the drain terminal of the front gate, the influence of interface states on theVt,fgwill be gradually covered. Therefore, when the stress time over 1000 s, the increase of theVt,fgtends to be saturated. In addition, when the stress condition changed toVbg=30 V, the maximum lateral electric field decrease while the negative vertical electric filed increase which contributes to the weakening of the impact ionization and the increase of the hole injection, as shown in Fig.9 (Vd=4.6 V, the solid line represents control group, and the dotted line represents modified group). Thus, the degradation ofVt,fgtends to be saturated and even begins to decline after just several hundred seconds.

For the modified devices, although the massive electrons captured in BOX have little effect on the front gate electric field during the back gate stress, they affect the front channel electric field distribution during the test process. On the one hand, it drives the major carriers closer to the front gate interface, thus enhancing the surface scattering of electrons and reducing the mobility of electrons. As a result, theGm,fgof modified devices suffered a huge decrease at the beginning of the stress. On the other hand, it results in the great increase ofVt,fgat the initial stage of stress by coupling effect.

Fig.8 Time dependence of degradation of Vt,fg and Gm,fg for devices suffered back gate HCI stress

Fig.9 Simulated lateral and vertical electric fields along front channel at different Vbg

3.3 Influence of irradiation

In order to explore the influence of irradiation on the hot carrier degradation of the modified devices, we classify the modified devices into three groups: 1) no treatment before stress; 2) irradiation with a total dose of 300 krad(Si) before stress; 3) irradiation at a total dose of 300 krad(Si) and annealing at 100 ℃ for 24 h before stressing. After 300 krad(Si) irradiation, the threshold voltage of back gate just exhibits a positive shift of about 0.9 V, while the control devices show a positive shift of about 5 V. The modified devices have a good resistance to radiation. In the following analysis, we will focus mainly on the effect of radiation on the hot carrier degradation of the modified devices, as shown in Fig.10 and Fig.11. For the modified devices, the degradation of bothVfgandGm,fgis more severe under HCI stress after 300 krad(Si) irradiation. Irradiation is known to create oxide trapped holes and interface states[19]. The radiation-induced trapped holes in the oxide which is the so-calledE′γcenter can anneal by “true annealing” via trapped hole emission or electron tunneling and “charge compensation”[20-22]. Thus, the irradiation induced trapped holes in the gate oxide can rapidly capture the hot electrons, resulting in the sharp degradation of the threshold voltage at the initial stage of stress. On the other hand, the irradiation-induced interface traps can reduce the barrier energy of electronφb, which can help the injection of the hot electrons. So, the irradiation enhanced hot carrier degradation occurs in the modified devices.

All in all, at the lowVfgstress, the trapped holes accelerate the degradation ofVfg. Both the trapped holes and enhanced elec-trons injection by interface states accelerate the degradation at highVfgstress while the electrons injection take control of the degradation. What’s more, the irradiation enhanced HCI degradation at lowVfgdisappears after the annealing at 100 ℃ for 24 h because the trapped holes in the oxide were almost all compounded during the annealing. But the annealing cannot totally eliminate this enhanced effect at highVfgstress due to its weakness to the interface states[23].

Fig.10 Time dependence of degradation of Vt,fg and Gm,fg for devices suffered HCI stress

Fig.11 Time dependence of degradation of Vt,fg and Gm,fg for devices suffered HCI stress before/after irradiation for Vfg=Vd=4.6 V

Similar to the process which the irradiation produces interface states[24], the composition of trapped holes and electrons during the stress can also induce interface states[25-27]. Lai[26]proposed that the annealing of the trapped holes by the electrons tunning from the silicon can produce interface states based on the so-called bond strain gradient (BSG) model. Wang et al.[27]also proposed that the trapped holes that near the interface can convert into interface states when capturing electrons in[28]. Whatever, these interface states induced by the combination of holes and electrons explain the rapid decline ofGm,fgfor the irradiated devices at the initial state of stress, as shown in Fig.10. And this enhanced degradation also eliminates after the thermal annealing due to the composition of the trapped holes during the anneal.

4 Conclusion

Comparing the hot carrier degradation by conventional and modified devices, the silicon nanoclusters in the modified devices trap a large number of electrons resulting in different effects on the hot carrier degradation in different cases by altering the electric field in the front and back channels. After irradiation, the modified devices are even subject to irradiation enhanced hot carrier degradation. This reminds the engineers who focus on the radiation resistance, whether they should adjust the silicon implant conditions to mitigate this effect though which may reduce the radiation resistance of the devices.