Frequency synthesizer for DRM/DAB/AM/FM RF front-end

Lei Xuemei Wang Zhigong Wang Keping Shen Lianfeng

(1School of Information Science and Engineering， Southeast University， Nanjing 210096， China)

(2College of Electronic Information Engineering， Inner Mongolia University， Hohhot 010021， China)

(3Department of Electrical Engineering， University of Washington， Seattle， Washington 98195， USA)

R adio broadcasting is a part of our lives that cannot be dismissed，but the traditional broadcast system has inherent shortcomings.The digital radio broadcasting shows the merits of anti noise， anti interferences，anti radio wave propagation weakness， and so on.Thus， the digital radio broadcasting receiver， being compatible with analog radio broadcasting，becomes a research focus.At present， the digital radio receivers of high quality are of less integration scale， expensive，and not compatible with analog radio broadcasting.Thus，the hot research topic of digital radio is to increase the integration scale， reduce the cost， and be compatible with analog radio broadcasting.

Digital radio mondiale(DRM)［1］/digital audio broadcasting(DAB)［2］/amplitude modulation(AM)/frequency modulation(FM)radio-frequency(RF)frontend is crucial in the design of the radio receiver.Thus，the double conversion low-IF DRM/DAB/AM/FM radio tuner architecture is adopted and the first intermediate frequency is set to be at 35.452 MHz［3］.The frequency grids of the DRM/DAB/AM/FM receiver are 1，3， 5，25， 64， and 128 kHz， respectively.The minimum frequency step is 1 kHz，and the maximum frequency step is 128 kHz.The receiving frequency range is from 148.5 to 1 496 MHz;thus the RF local oscillator(LO)tuning range must be able to cover from 35.600 5 to 1 572.452 MHz.

The traditional structure of the frequency synthesizer is the single loop， the single voltage-controloscillator(VCO)and its output signal is the output of the VCO［4］.Now，with the development of multi-standard communication systems，the frequency range becomes wider and wider so that the structure of the frequency synthesizer becomes more and more complicated， for example， including two VCOs in the loop［5-6］or adding the mixer and frequency divider to the outside of loop［7］.

In this paper，in order to generate the LO quadrature signals and cover the frequency range of the DRM，DAB，AM and FM，the structure of the frequency synthesizer for DRM/DAB/AM/FM is a single VCO and a single loop，supplemented with a multi-mode frequency divider(MMFD)， as shown in Fig.1.

Fig.1 Structure of DRM/DAB/AM/FM frequency synthesizer

1 Circuit Design

Referring to Fig.1， the frequency synthesizer consists of six parts:VCO，pulse swallow frequency divider(PSFD)，phase frequency detector(PFD)， charge pump(CP)，loop filter(LF)， and MMFD.The VCO must be wideband and of low-phase noise to meet the demands of the frequency plans， and all standards.The PSFD must be of high speed and wide band，high frequency division ratio to cover all the bands.The MMFD is designed aiming at high speed and wide-band low-phase noise to meet the demands of the LO.

1.1 Voltage-control oscillator

Fig.2 shows the schematic of the proposed oscillator［3］.It uses a double cross-coupled transconductance structure without tail current source，which is usually preferred in low-power and low phase noise applications.It consists of four parts，including a double cross-coupled transconductance circuit， an LC tank， two LC filter networks， and two isolation circuits for output nodes.The loss of the LC tank is canceled by the double cross-coupled transconductance circuit through generating a negative resistance.The LC tank consists of a spiral inductor， two MOS varactors， and a parallel switchable capacitor bank.The band width of the proposed VCO is controlled by the LC tank.The parallel switchable capacitor bank is a 4-bit coarse tuning element that changes the control codes，and two MOS varactors are fine-tuning elements that change the control voltages.Both the static output voltage and the static current in two sides are set by the size of the MOSFETs.The nominal output(V+，V-)bias point is 0.9 V and the circuit draws a static supply current of about 3.8 mA， which is enough for an oscillation.When the circuit begins to oscillate，it operates in the voltage-limited regime along the entire tuning range.The features of the supply current peaks coincide with the positive and negative peaks of the output voltage and thus vary at 2ω0.The average supply current is about 4.4 mA.

Fig.2 Schematic of the proposed VCO

1.2 Pulse swallow frequency divider

The architecture of the PSFD is shown in Fig.3.The programmable PSFD includes a divided-by-32/33 dualmodulus prescaler(DMP)，a 5-bit programmable swallow counter(SC)， an 11-bit programmable counter(PC)， and a control circuit(CC).The frequency division ratio of the DMP is controlled by the modulus control(MC)signal.The frequency division ratio of the SC and PC are changed by initially-set values ofPandS(P＞S).The CC controls the time sequence of the SC and PC and the modulus control(MC)signal through the swallow counter and the programmable counter.

Fig.3 Architecture of the PSFD

The DMP divides the VCO clockStimes in(32+1)mode， and(P-S)times in(32)mode.The total division factor of the divider isN=33S+32(P-S)=32P+S.The programmable counter withPvalues is between 32 and 4 095;the swallow counter withSvalues is between 0 and 31.So， when the synthesizer is locked， the output frequency of the VCO is:fosc=(32P+S)fref，wherefrefis the frequency of a reference signal.The frequency of the VCO output may contain 64 512 frequency points such as 1 024fref， 1 025fref，…， or 65 536fref， according to the values ofSandP.

To improve the performance， three types of DFF， i.e.SCL， TSPC and CMOS static flip-flops， are employed in the DMP［8］.Among of them the SCL is applied in the synchronous divided-by-4/5 counter since it can work at a higher speed，a wide band and an appropriate power consumption.A TPSC(true-single-phase-clock)［9］and two CMOS static flip-flops are applied in the asynchronous divided-by-8 counter;since the TSPC can work at a high speed and a low power consumption and a CMOS static flip-flop circuit structure，it can assure a good noise performance and keep a better interface with the next part simultaneously.

The SC consists of three blocks:a 5-bit programmable counter， a combination-logic circuit and a sample latch.The programmable counter is based on a chain of a 5-bit asynchronous preset static-logic divided-by-2 divider.The CLK signal of the SC is provided by the output signal of the proposed DMP.The input signals of the NOR gate are the output signals of all divided-by-2 dividers in the SC and the output signal of the NOR gate is the MC signal of the proposed DMP.

The PC consists of an 11-bit programmable counter，several combination circuits， and a latch.The programmable counter is based on a chain of 11-bit asynchronous preset static-logic divided-by-2 divider.Other circuits contain two NOR gates of three input ports，two NOR gates of four input ports， two NAND gates of three input ports， a NOT gate， and a latch.The CLK signal of the PC is provided by the output signal of the proposed DMP.The output signal is the final output of the proposal programmable PSFD.1.3 Multi-mode frequency divider

In order to convert the output signals of the VCO to LO quadrature signals as shown in Tab.1， a novel MMFD is given， and the architecture of the MMFD is shown in Fig.4.The MMFD includes a divided-by-5/6/7/8 divider， a divided-by-4/3/2/0.5 divider， a divided-by-4 divider，and a mode control circuit.

Tab.1 The frequency of 12 bands

Fig.4 Architecture of the MMFD

According to the tuning words of the system，the mode control circuits control the modes of the divided-by-5/6/7/8 divider and the divided-by-4/3/2/0.5 divider to choose a band.Finally， the synchronization 4 frequency divider is to generate the LO quadrature signals.

2 Measured Results

The chip of the frequency synthesizer is fabricated in a SMIC's 0.18-μm RF CMOS process.The chip photograph is shown in Fig.5.Its area is 1 425 μm ×795 μm， including pads and test circuits.

2.1 Measured results of voltage-control oscillator

Fig.5 Chip photograph of proposal frequency synthesizer

Thef-Vcurve of the proposed VCO is measured as a function of the control codes of the parallel switchable capacitor bank.The results are shown in Fig.6.The measured results show that its tuning range is 44.6% from 2.27 to 3.57 GHz， and its core power consumption is 6.16 mW under a 1.8 V power supply.

Fig.6 Measured f-V curve of the proposal VCO

The phase noise is measured by using an Agilent E4440A spectrum analyzer.To measure the phase noise，the control voltage is 1.4 V and the control-code is“0001”.The oscillation frequency is 3.385 GHz.The phase noise of the output is measured to be 120.22 dBc/Hz at 1 MHz offset from the carrier as shown in Fig.7.The FoM［10］of the proposed VCO is 182.6.

Fig.7 Measured phase noise of proposal VCO

2.2 Measured results of pulse swallow frequency divider

When the frequency of the input signal is 2.958 4 GHz and the frequency division ratio is 36 980，the proposed programmable PSFD works at the MF band and the output signal is 80 kHz.The measured result is shown in Fig.8.

Fig.8 Measured result in MF band

When the input voltage is minimum and the reliable operation of the above PSFD is guaranteed，the measured minimum input sensitivityVPPvs.the input frequency of the PSFD is plotted in Fig.9.The minimum input voltage of the frequency dividers is less than 0.95 V in the frequency range of 0.9 to 3.4 GHz.The minimum input signal peak， for the PSFD working at 3.4 and 0.9 GHz are 0.95 and 0.59 V， respectively.

Fig.9 Sensitivity measured from proposal PSFD

2.3 Measured results of multi-mode frequency divider

When the frequency division ratio is 32，the measured phase errors of LO quadrature signals are less than 3°， as shown in Fig.10.

2.4 Measured results of frequency synthesizer

When the frequency of the reference signal is 240 kHz and the frequency division ratio is 12 134，the phase noise of the output is measured to be-59.52 dBc/Hz at 10 kHz offset from the carrier as shown in Fig.11.

3 Conclusion

Fig.10 Output signals of multi-mode frequency divider

Fig.11 Measured phase noise of proposal frequency synthesizer

In this paper，a frequency synthesizer for DRM/DAB/AM/FM RF front-end is demonstrated in SMIC's 0.18-μm RF CMOS technology.The novel structure of the frequency synthesizer assures that one loop can cover the frequency range of 35.600 5 to 1 572.452 MHz and be compatible with the specification of radio standards of AM，F(xiàn)M，DRM and DAB.The measured results show that the performance of the frequency synthesizer meets the requirement of the DRM/DAB/AM/FM RF front-end.

［1］European Broadcasting Union.ETSI ES 201 980—2005 Digital radio mondiale(DRM);system specification［S］.Switzerland:Joint Technical Committee(JTC)Broadcast of the European Broadcasting Union(EBU)， 2005.

［2］European Broadcasting Union.ETSI EN 300 401—2006 Digital audio broadcasting(DAB)to mobile，portable and fixed receivers［S］.Switzerland:Joint Technical Committee(JTC)Broadcast of the European Broadcasting Union(EBU)， 2006.

［3］Zhou Jianzheng.Key-technologies research of DRM/DAB receiver RF front-end IC design［D］.Nanjing:School of Information Science and Engineering of Southeast University，2009.(in Chinese)

［4］Lee Seog-Jun， Kim Beomsup， Lee Kwyro.A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application［J］.IEEE Journal of Solid-State Circuits， 1997， 32(5):760-765.

［5］Zhou Jin， Li Wei， Huang Deping， et al.A 0.4-6-GHz frequency synthesizer using dual-mode VCO for softwaredefined radio［J］.IEEE Transactions on Microwave Theory and Techniques， 2013， 61(2):848-859.

［6］Osmany S A， Herzel F， Scheytt J C.An integrated 0.6-4.6 GHz， 5-7 GHz， 10-14 GHz， and 20-28 GHz frequency synthesizer for software-defined radio applications［J］.IEEE Journal of Solid-State Circuits， 2010， 45(9):1657-1668.

［7］Huang Deping， Li Wei， Zhou Jin， et al.A frequency synthesizer with optimally coupled QVCO and harmonicrejection SSBmixer for multi-standard wireless receiver［J］.IEEE Journal of Solid-State Circuits， 2011， 46(6):1307-1320.

［8］Lei Xuemei， Wang Zhigong， Wang Keping.A wideband low power low phase noise dual-modulus prescaler［J］.Journal of Semiconductor， 2011， 32(2):025011-1-025011-7.

［9］Yuan J， Svensson C.High-speed CMOS circuit technique［J］.IEEE Journal of Solid-State Circuits， 1989， 24(1):62-70.

［10］Moon Young-Jin， Roh Yong-Seong， Jeong Chan-Young，et al.A 4.39-5.26 GHz LC-tank CMOS voltage-controlled oscillator with small VCO-gain variation［J］.IEEE Microwave and Wireless Components Letters， 2009， 19(8):524-526.