Ultra-Low Power 1 Volt Small Size 2.4 GHz CMOS RF Transceiver Design for Wireless Sensor Node

Muhammad Yasir Faheem, Shun’an Zhong,, Abid Ali Minhas and Muhammad Basit Azeem

(1.School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China; 2.College of Computer and Information Systems, Al Yamamah University, Riyadh 11681, Kingdom of Saudi Arabia; 3.Department of Mechatronics Engineering, University of Engineering and Technology, Lahore Faisalabad 38000, Pakistan)

Abstract: Ultra-low power transceiver design is proposed for wireless sensor node used in the wireless sensor network (WSN). Typically, each sensor node contains a transceiver so it is required that both hardware and software designs of WSN node must take care of energy consumption during all modes of operation including active/sleep modes so that the operational life of each node can be increased in order to increase the lifetime of network. The current declared size of the wireless sensor node is of millimeter order, excluding the power source and crystal oscillator. We have proposed a new 2.4 GHz transceiver that has five blocks namely XO, PLL, PA, LNA and IF. The proposed transceiver incorporates less number of low-drop outs (LDOs) regulators. The size of the transceiver is reduced by decreasing the area of beneficiary components up to 0.41 mm2 of core area in such a way that some functions are optimally distributed among other components. The proposed design is smaller in size and consumes less power, <1 mW, compared to other transceivers. The operating voltage has also been reduced to 1 V. This transceiver is most efficient and will be fruitful for the wireless networks as it has been designed by considering modern requirements.

Key words: low-drop outs (LDOs); transceiver; metal oxide semiconductor field effect transistor (MOSFET); wireless sensor networks (WSN)

Wireless sensor network (WSN) applications are required for the ideal power consumption in a processing of system. As the preview of WSN grows day by day, more reliability, compatibility, and efficient power consumption are needed for its applications. The nodes are important in every sensor network and the transceiver is its major part. The radio frequency (RF) transceivers also have significant role in the meadow of wireless sensor networks[1-2]. We can use passive front end for transceivers in mesh networks[3]. The problems were power consumption and overall efficiency of the transceiver. “Integrated resonant matching network” was used to achieve better power consumption. In large complex system designs, “hierarchical concurrent flow graph” (HCFG) approach can be used for a good performance[4]. As wireless networks operate on some voltage, they have to be battery operated or attached with some fixed supply voltage. These multiple voltage sources increase the heat in network and strongly requires a heating controlled mechanism to protect the comments from burning or malfunctioning. Furthermore when we take about overhead, a digital transceiver and Manchester coding scheme has been used which helps in decreasing the overhead of synchronization[5]. Overhead can also be reduced by planting two inductors of 1.2 nH and 8 nH using some schematic[6]where turn on time comes down to 10 μs and efficiency can be increase up to 17%. “Zinc-air coin cell” can be used with printed battery technologies to address battery lifetime concerns[7]. To increase the battery life time of a transceiver physical layer architecture, which reduced the power consumption of the transceiver and also increased transceiver performance in all short range communication, was proposed[8].

The dual conversion architecture and Trans-conductance linearization technique using a mixer based on current mirror amplifier was usedto achieve better performance of the transceiver[9], where “self-aligned gate field effect transistor” SAGFETs can be used to make the transceiver less expensive[10]. The unbalanced structure can be replaced with differential ones using the same chip for better power consumption[11]. Researchers have designed a very low power wearable transceiver for medical specialist[12]in which we need to reduce the wake up time of the transceiver by using wake frame scheme. Therefore, if a node wants to communicate with a sleeping transceiver, it sends the wake up signal which puts the transceiver in a communicating mode that is called wake up signal scheme[2].

1 Problem Statement

In the last few years, applications of wireless sensor networks have been increased and consequently ithas become necessary to decrease the cost of sensor nodes. At the same time many applications need small sized sensor nodes. Most of the applications require the sensor nodes to be placed in an inactive state for a long time. Combining all these, a node with a small size, small cost and low power consumption has to be designed keeping in mind that there must not be any compromise on the functionality of the node. While decreasing the size of the node, the size of the transceiver has to be reduced as well. The current challenge is to design low cost, small sized transceivers that must consume lower power. In Ref. [13] there was no switch used for separating the transmitting and receiving nodes to increase the battery life. We need to separate the nodes of the transceiver using a switch and make some other changes in the circuitry of blocks to reduce the power consumption of the transceiver.

2 Proposed Design

The proposed design of ultra-low power and small size 2.4 GHz CMOS RF transceiver design for WSN is comprised of five major blocks which are low noise amplifier (LNA), intermediate frequency (IF), phase lock loop (PLL), power amplifier (PA) and crystal oscillator (XO).

The proposed design is novel due to its less number of internal and external components it also includes the power efficient power amplifier and different modes which can be automatically controlled by switches.

We have proposed a solution which overcomes all the problems which have been discussed already. The block diagram of the proposed RF transceiver is shown in Fig.1.

Fig.1 Block diagram of proposed transceiver design

This design is miniaturized due to its efficient circuitry. The problem related to area and power consumption is well treated using the concept of balancing and biasing. When En3and En2pins are enabled, the transceiver will be in receiving mode and the antenna receives the data and gives it to the LNA module. If En1and En2pins are enabled, then the transceiver will be in transmitting mode and the antenna transmits the data after taking it from the PA module. Design of each module is given below: In Fig.2 the image of complete design/circuitry of an ultra-low power and small sized CMOS RF transceiver from advanced designed system (ADS) Tools by Agilent technologies is presented along with the connectivity of modules.

Fig.2 Complete transceiver circuit of all blocks

2.1 Power consumption

Power consumption depends on two types of power. The first one is instantaneous power (Pi) measured in Watts and the second one is power used over the period of time (Pt) measured in Watts-hours. In CMOS circuits there are three types of power consumption/dissipation which can be reduced by applying critical thinking on them as follows:

Static power consumption depends on supply voltage (Vcc) and current in to the components (Icc) according to

Ps=VccIcc

(1)

wherePsis static power.

Dynamic power consumption can be calculated by adding capacitive load and transient power consumptions only when transistors change their status from logic to another.

Capacitance power dissipation can be calculated by using the following factors multiplication.

(2)

wherePLis power consumption of capacitive load,CLis capacitance load,VCCis supply voltage,FOis output signal frequency,NSWis total no of output switching.

In the proposed design the power consumption reduced up to 1 mW due to less number of components, as there is no inductor present in proposed transceiver, where width and length of MOSFET’s also reduced up to pico meter. Less number of LDO’s consume less power.

2.2 XO and PLL

XO and PLL enables the transceiver to be in transmitting mode or in receiving mode.

XO job provides the reference input frequency to the frequency synthesizer. The wake up time of crystal oscillator is about 1 200 μs, operating voltage is 1 V and its supply current is 18 μA. XO module is directly connected to the crystal which is an external component of the transceiver and takes the reference frequency from it. After that, it creates oscillations under a certain threshold level using a feedback loop. XO also controls the amplitude of oscillation. The complete circuitry and working directions are shown in Fig.3.

There are three major sub blocks in PLL module; these are phase detector, voltage control oscillator and a band pass filter. PLL module generates the differential output signal of 2.4 GHz frequency and its output connected to the input of next two modules includes PA and LNA. Wake up time of this module is less than 20 μs while supply current is 611 μA and operating voltage is 1 V.

2.3 PA

There is a push pull stack in this module, which amplifies (increase the strength) the signal before transmitting it through externally attached antenna. A sub block of FM “frequency modulation” takes input bits and attaches them before the stack.

Schematic shown in Fig.4 is enabled only when the transceiver is in transmitting mode. Effective output power of the transceiver using power amplifier is calculated as[1]

(1)

whereVout.maxis swing voltage andRloadis load impedance which is fixed at 50 Ω.

2.4 LNA and IF

LNA and IF are enabled when the transceiver

is in receiving mode. Cross coupled amplifier is called Gilbert cell. Quadrature double balanced gilbert cell down mixer and LNA are coupled together. LNA is directly connected with PLL and IF and by using a switch, we can convert the transceiver in both modes. The switch is directly attached with LNA, PA and band pass filter. The input voltage has been set to 1 V with 898 μA supply current and wake up time of LNA adjusted to around 20 μs.

There are two sub blocks in IF module; the first one is band pass filter which is used for channel selection. In the proposed design it is a 3rdorder Chebyshev filter. The second part is a FM-demodulator. At the end of this circuitry, there are numeric sink block which receives all the data at the receiver end.

Fig.3 Schematic of the crystal oscillator and PLL

Fig.4 Schematic of the PA push pull stack

Fig.5 Schematic of the LNA and IF

2.5 Miniaturization

By using lesser number of components, lesser number of enable pins, and decreasing the size of MOSFET’s by reducing their width and length in such a manner that output is not effective during processing, less number of LDO’s regulators are used, since we reduced it from five to three which automatically decreases the size of the transceiver. The conceptual diagram is shown in Fig.6 which can be described easily and shows the difference between previous work and our work.A1,A2,A3,A4,A5,A11,A22andA33are all represents the size of LDO’s.AtotandAtot neware represents the sizes of previous and proposed transceiver using some constantK.

Fig.6 Conceptual diagram of miniaturization

From Fig.6 we have

(AXO+APLL+A22)+(ALNA+AIF+A11)+
(APA+A33)=Atot new

(2)

If

A11=A22=A33=A1=A2=A3=A4=A5=K

PuttingKin Eq.(2) we get

(AXO+APLL+ALNA+AIF+APA+3K)=Atot new

(3)

From Fig.6 we also have

(AXO+A1)+(APLL+A2)+(ALNA+A3)+
(AIF+A4)+(APA+A5)=Atot

(4)

PuttingKin Eq.(4) we get

(AXO+APLL+ALNAAIF+APA+5K) =Atot

(5)

By the comparison of Eq.(3) and Eq.(5) we get

Atot-2K=Atot new

(6)

Eq.(6) shows that

Atot new

(7)

Hence, Eq.(7) verifies that the proposed transceiver has a much smaller area compared to the previous one.

2.6 Cost and reliability

The cost of the transceiver is directly proportional to the size of the device.

Size of transceiver∝ Cost of transceiver

Miniaturization of the transceiver defiantly decreases the size of the chip, so the cost of the transceiver automatically reduces according to the above equation.

Budget analysis of some components which are very important and major on the budget perspective of our transceiver are shown in Fig.7.

The graph shows four important components which play a vital role in transceiver fabrication are summer, mixer, power supply, modulator/demodulator and band pass filter and the quantity of these components are two, five, one, two and two respectively from bottom to top it can be clearly seen the linear relationship between components. On the other hand, the most expensive component is (band pass filter) BPF and summer is the cheapest, where MOD represents the modulator, MIX is a mixer and PWR is the supply power.

Fig.7 Budget analysis of some important components of transceiver

Reliability also means it has a long life time; as our proposed solution utilizes less power compared to previous work which has an increased battery life time. This characteristic of the transceiver will increase efficiency in even worst condition i.e. even a smaller amount of energy in the battery will not affect the performance of transceiver. The transceiver is designed at 2.4 GHz operating level which comes under the heading of ISM unlicensed band, so its compatibility within this band is certain for the users.

3 Design Implementation and Results

Design and the implementation of the proposed transceiver are made by ADS tools where after putting different values on different stages we verified the results. There are different figures and tables in this section to analysis the true picture of the improved results.

All the building blocks of the transceiver are well tested separately where after successfully testing the blocks are assembled together for transceiver test on 2.4 GHz frequency. S-parameter shows the electrical behavior of the circuit using 50 Ohm load.

In Fig.8 S-parameter and frequency is shown that the frequency starts oscillation from 2.4 GHz and stops on 3.4 GHz. Which shows the compatibility and feasibility range of all the modules, as this assessment includes all the blocks. In vertical and horizontal the values of S-parameter in dB and frequency in GHz is presented.

Fig.8 Graph between S-parameters & frequency in GHz

The operating frequency of the transceiver measured in 100 ns is 2.4 GHz on different time of interval as shown in Fig.9. The starting time of proposed transceiver is also 100 ns and it can be seen that in the first 100 ns by getting some samples the operating frequency is exactly which is demanded.

Fig.9 Operating frequency vs time

Fig.10 shows the graphical representation between mixer and frequency as the harmonic balances stable at the 2.4 GHz. It can be concluded from the graph that mixer is working properly at 2.4 GHz as it linearly approaches to the operating frequency. HB is calculated for the nonlinear elements in the circuit including the mixer. The maximum value of the HB is 1 when circuit will start operation using 2.4 GHz frequency.

Fig.10 Harmonic balance between frequency & mixer

The important measurements and their values with specific units which we have obtained in our research work are shown in Tab.1.

Tab.1 Important parameters and their values

This transceiver is operating at 2.4 GHz which is much higher as it before and power consumption is less than 1 mW which also improved.

The supply current of each module is calculated separately as shown in Fig.11 there an almost linear relationship between all blocks in the aspect of current consumption. Furthermore, the graph shows the current supplied from lowest LNA to highest IF.

Fig.11 Proposed transceiver blocks supply current

Tab.2 shows the comparison of some parameters between the proposed transceiver and existing transceivers, where the difference clearly highlights that the proposed transceiver is much better before.

There are different methods used for transceiver design which produce different results, to differentiate this, a graph of comparison between

Tab.2 Few comparisons between proposed and pervious researches

Fig.12 Comparison of results of different methods

existing method results and proposed method result is shown in Fig.12, which clearly shows the efficiency, cost and external components strength in design. Power amplifier is directly connected to 1.2 V to get the maximum power efficiency as the power amplifier is the key source of power consumption.

4 Conclusion

We proposed a small sized, ultra-low power 2.4 GHz RF CMOS transceiver design for WSN applications. The proposed transceiver consumes <1 mW power at 2.4 GHz operating frequency, where it contains five modules which are XO, PLL, PA, LNA, and IF. The cost of the transceiver decreases up to one dollar due to miniaturization and the chip area of core circuitry is 0.41 mm2. The intelligent design gives the data rate 45 Kbps with 10 m range. The load is fixed at 50 Ω and it operates on 1 V input voltage. There are four external components and the LDO’s are reduced from five to three. In simulation results, it also intuited that the number of components decreases due to this new design. Moreover, the enabler pins are also reduced from five to three.