適于16納米及以下技術(shù)代的新型器件研究—2013年度總結(jié)報告

黃如

摘 要：針對半導(dǎo)體器件進入16 nm及以下技術(shù)代將面臨的可制造性難度大、功耗限制、性能退化等核心問題，重點開展了新型圍柵納米線器件、新型超低功耗TFET器件、高遷移率溝道器件、閃存器件以及納米尺度器件的可靠性及漲落性研究，為新型器件在將來納米集成電路中的應(yīng)用奠定了基礎(chǔ)。在納米線器件研究方面，設(shè)計了側(cè)墻轉(zhuǎn)移法和TMAH各向異性腐蝕法制備超精細硅納米線的可控工藝，并進行了實驗驗證；建立了自限制氧化法硅納米線制備工藝理論模型，可對工藝進行精確預(yù)測；提出了一種原子層摻雜結(jié)構(gòu)可有效調(diào)控納米線器件的閾值電壓，同時避免了遷移率的損失；研究了納米線器件中的GIDL電流機制，提出了抑制GIDL電流的優(yōu)化方法；提出了一套新的器件-電路優(yōu)化設(shè)計方案，針對納米線器件在數(shù)字電路、模擬/射頻電路中的應(yīng)用分別進行優(yōu)化設(shè)計，得到了相應(yīng)的設(shè)計窗口。在新型低功耗器件研究方面，提出了一種結(jié)調(diào)制型TFET，顯著提升了器件的亞閾特性和開態(tài)電流；通過引入pocket層進一步優(yōu)化了器件結(jié)構(gòu)，實驗制備獲得了非常低的SS（36mV/dec）和高的開態(tài)電流。提出了一種隧穿觸發(fā)注入場效應(yīng)晶體管，能同時實現(xiàn)高開態(tài)電流、低泄漏電流和陡直的亞閾特性。在納米尺度MOS器件的可靠性與漲落性研究方面，提出了由AC NBTI引入的工作循環(huán)間漲落的兩種重要來源的表征方法，實驗發(fā)現(xiàn)了AC NBTI退化及其漲落的頻率依賴性的新現(xiàn)象，建立了物理模型。研究了多柵新器件中的AC RTN，發(fā)現(xiàn)比平面器件中的AC RTN活躍程度增強。提出了一種新的AC RTN表征方法，可拓展RTN的柵壓探測范圍區(qū)域。在高遷移率器件研究方面，提出了兩種氮等離子體處理方法來提高柵介質(zhì)/溝道界面質(zhì)量，進行了實驗驗證；采用P/Sb共注入技術(shù)既有利于提升NiGe薄膜質(zhì)量，也利于電學(xué)性能的提升。針對工藝集成中的關(guān)鍵工藝，對鍺刻蝕技術(shù)進行了實驗研究，得到了適于鍺的優(yōu)化刻蝕條件；在此基礎(chǔ)上建立了一個線性RIE刻蝕模型，得到了實驗驗證；完成了Ge NMOS和PMOS器件的工藝制備，分析了不同鈍化技術(shù)對Ge器件的影響。在新型閃存器件研究方面，針對TFET-Flash器件的優(yōu)化器件設(shè)計結(jié)構(gòu)，并制備出TFET-FLASH器件，測試結(jié)果表明，與傳統(tǒng)閃存器件相比，其編程效率提高100倍左右。針對三維閃存技術(shù)面臨的問題，提出了一種三維圍柵結(jié)構(gòu)的TFT陷阱閃存及其NAND型陣列架構(gòu)，可有效提高閃存存儲密度和降低單元成本；并制備了雙層圍柵TFT閃存原型。測試結(jié)果表明，該新型圍柵結(jié)構(gòu)TFT閃存在電流開關(guān)比、亞閾斜率、遷移率、編程和擦除速度等方面均獲得較大改善，并具有多值存儲的潛力。

關(guān)鍵詞：納米尺度 硅納米線器件 低功耗 高遷移率 閃存器件

Abstract：To overcome the problems of manufacturability， power and performance degradation in conventional semiconductor devices when entering 16 nm technology node and beyond， a series of novel devices are investigated for future nanoscale IC applications， including gate-all-around nanowire FETs， ultralow-power TFETs， high-mobility channel devices， Flash memory devices， as well as the device reliability and variability. For nanowire FETs： novel spacer transfer and TMAH etching techniques for controllable nanowire formation are proposed and demonstratedtechnology models for self-limiting oxidation of nanowires are developed for precision process predictionan atomic doping structure is proposed for nanowire threshold voltage control and mobility improvementGIDL in nanowire FETs are studied for its further suppressiona new design methodology for device/circuit optimizations is proposed and demonstrated in nanowire FETs for digital and analog/RF applications. For novel ultralow-power devices： a junction-modulated TEFT is proposed for subthreshold and Ion improvementrecord SS of 36mV/dec and high current are demonstrated by introducing pocket structuresa tunneling-injection FET is proposed for high-Ion， low-Ioff and steeper SS. For device reliability and variability： characterization methods for AC NBTI induced dynamic variability are proposedthe frequency dependence of AC NBTI degradation and variation are observed and modeledAC RTN in multi-gate devices is found have enhanced activity than that in planar FETsa new AC RTN technique is proposed for expanding RTN test window. For high-mobility devices： two plasma techniques for improving gate stack interface are proposed and demonstratedP/Sb co-implantation technique is adopted for improving NiGe film quality and electrical performanceGe etching is experimentally studied and modeled for process optimizationGe NMOS and PMOS devices are fabricated with various passivation techniques. For novel flash memory devices： a new TFET-FLASH device is proposed and fabricated， which have 100x improvement in programming efficiencya 3D gate-all-around TFT flash and its NAND array are proposed for increasing density and reducing costtwo-level gate-all-around TFET prototypes are fabricated， which exhibit enhancement in ON/OFF ratio， SS， mobility， programming/erasing speed and the potential for multi-bit storage.

Key Words：Nanoscale；Silicon Nanowire Transistor；Low Power；High Mobility；Flash

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