Research on Non-Ideal Factors of Segmented-Capacitor DAC in CMOS Image Sensor*

SUN Quan，YAO Suying，XUWenjing，NIE Kaiming，XU Jiangtao

(School of Electronic Information Engineering，Tianjin University，Tianjin 300072，China)

Research on Non-Ideal Factors of Segmented-Capacitor DAC in CMOS Image Sensor*

SUN Quan，YAO Suying，XUWenjing，NIE Kaiming，XU Jiangtao*

(School of Electronic Information Engineering，Tianjin University，Tianjin 300072，China)

segmented－capacitor digital analog converter(SC DAC)is usually used in CMOS image sensor to generate a ramp reference voltage.Precise relationships between conversion resolution and non－ideal factors segmented－capacitor digital analog converter are derived.These non－ideal factors consist of coupling capacitormismatch，binary－weightedcapacitormismatch and parasitic effects.Initially，based on the study of SC DAC operation principle，mathematical models are established.Then the effects of non－ideal factors on SCDAC are analyzed.Simulation andmeasurement results verify the theoretical analysis.These precise relationships serve as a guideline for the design of SC DAC.

microelectronics and solid electronics;segmented－capacitor DAC;capacitormismatch;parasitic;conversion resolution

Nowadays CMOS image sensors are becoming competitive with regard to charge couple devices(CCD)，and they have been applied inmany areas，such as digital photography，industrial vision，medical and space applications［1－2］.Single Slope ADC is widely applied in CMOS image sensor serving as the on－chip column－parallel ADC due to its low power costand low FPN contribution.DAC is a critical building block in the single slope ADC，which can determine the ADC’s linearity，and the charge－redistribution DAC(CR DAC)is almost exclusively used in the single slope ADC［3－5］.

Although the CR DAC offers excellent properties，large chip area is an issue in higher digital resolution. For example，to achieve 12－bit SC DAC，4096(212)unit capacitors are required.To solve this problem，segmented－capacitor DAC(SC DAC)with a coupling capacitor connecting two binary weighted capacitor arrays is proposed［6］，which just needs 2N/2+1unit capacitors.Compared with traditional CR DAC，the number of capacitors in SC DAC decreases exponentially，which results in higher speed，lower power consumption and smaller chip area.As a consequence，SC DAC iswidely used at present［7－9］.

The available resolution of SC DAC ismainly determined by capacitormismatch and the parasitic effects on each side of the coupling capacitor.Therefore，it is essential to obtain precise relationships between conversion resolution and non－ideal factors.In Ref.［6］，the research work was focused on the coupling capacitor mismatch without considering binary weighted capacitormismatch and parasitic effects.In Ref.［10］，a 14 bit DAC，designed in a CMOS 0.35μm process and based on segmented arrays of switched capacitors controlled by a dynamic element matching algorithm.This DAC features an INL lower than 0.5 LSB at 5 MHz，and dissipates less than 7 mW.In Ref.［11］，an error correction method of coupling capacitormismatch was reported，regardless of binary weighted capacitormismatch and parasitic effects.In Ref.［12］，capacitormismatch and the parasitic effects of an improved SCDAC were analyzed，but only qualitative conclusions were deduced.In this paper，precise relationships between conversion resolution and non－ideal factors are proposed.These non－ideal factors consist of coupling capacitor mismatch，binary weighted capacitor mismatch and parasitic capacitors. Simulation and experimental results are in favor of the proposed theory，which can be applied to the design of SC DAC.

1 Architecture of SC DAC

Fig.1 shows the architecture of N－bit SC DAC which has two capacitor arrays(LSB NET and MSB NET)connected by a coupling capacitor.The schematic of SCDACwhen N is even is depicted in Fig.1(a)，and the schematic when N is odd is shown in Fig.1(b).According to Fig.1，N is the conversion resolution，C is the minimum capacitance used for the least significant bit，VREFis the reference voltage，and VOUTis the DAC output voltage.The N－bit SCDACworks as follows.Initially，all switches are thrown to ground，so that all capacitors are discharged.Next，switch Srstturns off，and switches SNS1are thrown to ground or VREFaccording to digital codes.The output voltage(VOUT)of SC DAC can be expressed as

Fig.1 Architecture of N bit SCDAC

where Biis the input digital code of SC DAC.When Biis logic‘high’，Siis thrown to VREF;otherwise，Siis thrown to ground.

The Thevenin’s equivalent circuit of N－bit SCDAC in Fig.1 is shown in Fig.2，where CLSBstands for the total capacitance value of LSB NET，CMSBstands for the total capacitance value of MSB NET，CCis the coupling capacitor，VLrepresents the equivalent voltage of LSB NET，and VMrepresents the equivalent voltage of MSB NET.When N is even，we have

When N is odd，we can obtain

Fig.2 Thevenin’s equivalent circuit of SCDAC

2 Analysis of Non－Ideal Factors

2.1 Analysis of Parasitic Capacitors

Fig.3 shows the Thevenin’s equivalent circuit of SC DAC considering parasitic capacitors.CPLis the total parasitic capacitors，including the left plate of CCand the up plate of CLSB.CPMrepresents the total parasitic capacitors，including the right plate of CCand the up plate of CMSB.

Fig.3 Thevenin’s equivalent circuit of SCDAC considering parasitic capacitors

According to superposition principle，VOUTis the sum of VOUTL(VM=0)and VOUTM(VL=0).

Considering Eq.(12)and Eq.(13)，VOUTis obtained:

A.N is even

(1)When the digital codes of LSB NET change and those of MSB NET do not change，the Thevenin’s equivalent voltage difference between neighboring codes according to Eq.(5)and Eq.(6)can be expressed as follows:

Combining Eq.(14)and Eq.(15)，the voltage difference of VOUTbetween neighboring codes is given by

Obviously，in this case，the step heights of the SC DAC output voltage(Δ)are consistent，hence，Δis defined as the new LSB.

(2)When the digital codes of MSB NET change，the digital codes of LSBNETmust change from all‘1’to all‘0’，then the Thevenin’s equivalent voltage difference between neighboring codes is

Applying Eq.(17)to Eq.(14)，the voltage difference of VOUTbetween neighboring codes is expressed as Eq.(18)，which indicates that the step heights of the SC DAC output voltage()are concordant in this case.

Comparing Eq.(16)with Eq.(18)，it is obvious that although the step heights of the SC DAC output voltage are consistent respectively in the two casesmentioned above，voltage difference exists between them，which results in the deterioration of DNL.Take 8－bit SC DAC with parasitic capacitors for an example，as shown in Fig.4.During the period of SC DAC conversion，the digital codes of MSB NET will change 2N/2－1times，so the integral nonlinearity(INL)is given by

Fig.4 8－bit SC DAC with parasitic capacitors

In order to realize N－bit SC DAC，INL must be less than LSB/2，and then we have

According to Eq.(2)，Eq.(3)，Eq.(4)，Eq.(16)，Eq.(18)and Eq.(20)，Eq.(21)can be obtained.

From Eq.(16)，Eq.(18)，Eq.(20)and Eq. (21)，it can be seen that CPMhas no effect on the linearity of SC DAC while CPLdeteriorates the linearity.

(B)When N is odd，applying the similar analysis method above to this situation，and then we have

According to Eq.(21)and Eq.(22)，the curve which depicts themaximum allowable parasitic capacitor for a given resolution can be drawn，as shown inFig.5，where N≤12 because of the limitation of passive components.From Fig.5，it is found that themaximum allowable parasitic capacitor CPLdecreases with the increasing of resolution.

Fig.5 the relationship between resolution and the maximum allowable parasitic capacitor

2.2 Analysis of Coupling Capacitor Mismatch

The Thevenin’s equivalent circuit of SC DAC with coupling capacitor mismatch is as shown in Fig.2，in which the coupling capacitor CCis expressed as

Whereδ(－1＜δ＜1)is the maximum mismatch ratio.The analysis method of coupling capacitor mismatch is the same as parasitic capacitors，and the only difference is that CPL=CPM=0.Therefore，considering CPL=CPM=0，Eq.(16)and Eq.(18)can be simplified as

Applying Eq.(2)，Eq.(3)，Eq.(23)，Eq.(24) and Eq.(25)to Eq.(20)，Eq.(26)is derived.When N is odd，we have Eq.(27).From Eq.(26)and Eq. (27)，F(xiàn)ig.6 is acquired，which reflects the relationship between resolution and the maximum permissible coupling capacitormismatch.According to Fig.6，it can be seen that not only the maximum permissible coupling capacitor mismatch can be obtained according to the resolution，but also the available resolution can be predicted conversely.

Fig.6 the relationship between resolution and themaximum permissible coupling capacitormismatch

2.3 Analysis of BinaryWeighted Capacitor Mismatch

The architecture of N－bit weighted capacitor SC DAC is shown in Fig.1，where each weighted capacitor is assumed to be off by a factor of(1+ei)from the ideal value due to process variations.

Ci=2i－1C(1+ei)，i=1…N，C0=C(1+e0)(28)

Because of the randomness of binary weighted capacitor mismatch，we can suppose that both CLSBand CMSBare fixed values［13］，then Eq.(29)and Eq.(30) can be obtained.

Whereξ(0＜ξ＜1)is themaximum mismatch ratio. Considering that CLSBand CMSBare fixed values，Eq.(2)，Eq.(3)，Eq.(4)，Eq.(7)，Eq.(8)and Eq.(9)are all suitable for binary weighted capacitormismatch analysis. The output voltage of SC DAC with binary weighted capacitormismatch can be derived by taking CPL=CPM=0 in Eq.(14).

When N is even，VLand VMcan be expressed as Eq.(32)and Eq.(33)according to Eq.(28).

Combining Eq.(2)，Eq.(3)，Eq.(4)，Eq.(32) and Eq.(33)with Eq.(31)，we have

The ideal DAC output(VOUT，ideal)and ideal LSB(LSBideal)can be obtained by taking ei=0 for all i in Eq.(34).

The error voltage is the difference between ideal and actual output voltages:

In order to realize N－bit SC DAC，INLmust be less than LSBideal/2，then

From Eq.(29)，Eq.(30)and Eq.(37)，we can see that VOUT.errorwill take maximum value when eiare expressed as

Applying Eq.(39)to Eq.(37)，themaximum value of VOUT，erroris given by

Combining Eq.(38)with Eq.(40)，Eq.(41)is derived.When N is odd，we have Eq.(42).The curve of the relationship between the maximum allowable binary weighted capacitormismatch and resolution are shown in Fig.7 according to Eq.(41)and Eq.(42).Therefore，with the increasing of resolution，themaximum allowable binary weighted capacitormismatch decreases exponentially.

Fig.7 the relationship between themaximum allowable binary weighted capacitormismatch and resolution

3 Simulation and Measurement Results

3.1 Simulation Results

In order to verify the precise theory derived above，simulations are conducted with Spectre.The following simulation takes8－bit SCDAC as an example.The schematic of the ideal 8－bit SC DAC is shown in Fig.8，where themain parameters are as follows:VREF=3.3 V，C=150 fF，CC=160 fF.

Fig.8 8－bit SC DAC

(A)Simulation results of 8－bit SC DAC with parasitic capacitors.

The parasitic capacitor CPLis added in the ideal 8－bit SC DAC，as shown in Fig.9.As for an 8－bit SC DAC，considering Eq.(21)，the capacitance of CPLmust be less than 4%C.When CPL=4%，C=6 fF，as can be seen from Fig.10，DNL of SC DAC with parasitic capacitors deteriorates when the codes of MSB NET change and INL is less than LSB/2 if the value of CPLis selected by Eq.(21)，which are in consistent with the theoretical analysis.

Fig.9 8－bit SCDACwith parasitic capacitor

(B)Simulation results of 8－bit SC DAC with coupling capacitormismatch.

Supposing the coupling capacitor CCof ideal 8－bit SC DAC has a factor of(1+δ)，the equivalent circuit is depicted in Fig.11.According to Eq.(26)，the allowable maximum coupling capacitor mismatch|δ|is 0.35%. Whenδ=0.35%，CCis calculated to be 160.56 fF;otherwise，whenδ=－0.35%，CC=159.44 fF.From Fig. 12 and Fig.13，it is concluded that if the coupling capacitormismatch is selected by Eq.(26)，INL is less than LSB/ 2，which is in positive to the theoretical analysis above.

Fig.10 DNL and INL of 8－lib SCDACwhen CPL=4%C

Fig.11 8－bit SCDAC with coupling capacitormismatch

Fig.12 DNL and INL of8－lib SC DACwhen coupling capacitormismatchδ=0.35%

Fig.13 DNL and INL of8－lib SC DACwhen coupling capacitormismatchδ=－0.35%

(C)Simulation results of8－bit SCDACwith binary weighted capacitormismatch.

Each weighted capacitor in Fig.8 is assumed to be off by a factor of(1+ei)，which can be expressed as Eq. (39).The permissiblemaximum binary weighted capacitormismatch in Eq.(39)is 0.4%from Eq.(41).Fig.14 illustrates that INL of SC DAC is less than LSB/2 when the value ofξis in accordancewith Eq.(41)，which is also in favor of the theoretical analysis.

Fig.14 INL of8－bit SCDACwith binary weighted capacitormismatch

3.2 Measurement Results

According to the theoretical analysis and simulation results discussed above，to realize an 8－bit SC DAC，the ranges of non－ideal factors are obtained.In order tomeet the range requirements of the coupling capacitor mismatch and the binary weighted capacitor mismatch，thevalue of unit capacitor must be larger than 200 fF according to the capacitormismatch data in process characterization report.When the unit capacitor is selected to be 200 fF，the parasitic capacitor CPLis 3.8%C，which iswithin the error range.

The 8－bit SCDAC is applied to a single－slope ADC which is fabricated in GSMC 0.18μm 1P4Mstandard CMOS technology.The chip micrograph is given in Fig. 15.The FFT spectrum of the designed ADC with 1.27 Hz input frequency at 5.2 ksample/s sample rate is shown in Fig.16.It is obvious that the signal－to－noise and distortion ratio(SNDR)and the effective number of bit(ENOB)are 50.73 dB and 8.1 bit respectively.Considering SCDAC is a component of the ADC，there is no doubt that the resolution of SC DAC reaches 8 bit.Consequently，the proposed precise relationships are applied to the design of SC DAC successfully.

Fig.15 Chip micrograph of single－slope ADC

Fig.16 FFT spectrum for input frequency of1.27 Hz at5.2 ksample/s

4 Conclusion

In this paper，precise relationships between conversion resolution and non－ideal factors are derived.These non－ideal factors consist of coupling capacitor mismatch，binary weighted capacitormismatch and parasitic capacitors.According to the simulation andmeasurement results，it is obvious that the precise relationships can be applied to the design of SC DAC.Therefore，the precise relationships serve as a guideline for the design of SC DAC.

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Sun Quan(1979－)，male，Ph.D.candidate，main research interest is design of CMOS image sensor，sunquan98@ sina.com;

Yao Suying(1947－)，female，professor and Ph.D.candidate supervisor，main research interests are design of CMOS image sensor and application specific integrated circuit，syyao@tju.edu.cn;

Xu Jiangtao(1979－)，male，Associate professor，main research interest is design of CMOS image sensor，xujiangtao@tju. edu.cn.

CMOS圖像傳感器中分段電容DAC非理想因素研究*

孫權(quán)，姚素英，徐文靜，聶凱明，徐江濤*
(天津大學(xué)電子信息工程學(xué)院，天津300072)

CMOS圖像傳感器信號處理中通常采用分段電容DAC產(chǎn)生斜坡參考電壓。研究了分段電容DAC精確的電容失配及寄生與其轉(zhuǎn)換精度的關(guān)系式。基于對分段電容DAC工作原理的研究，導(dǎo)出了電容失配及寄生模型;針對其分?jǐn)?shù)橋接電容失配、各二進(jìn)制電容間的失配及寄生電容問題進(jìn)行了理論分析;對分段電容DAC進(jìn)行非理想因素仿真，設(shè)計了一個采用分段電容DAC的10位單斜ADC并對其進(jìn)行測試，仿真和測試結(jié)果均驗證了理論分析的正確性。上述理論分析結(jié)果可作為分段電容DAC的設(shè)計指導(dǎo)。

微電子學(xué)與固體電子學(xué);分段電容DAC;電容失配;寄生;轉(zhuǎn)換精度

TN402

A

1004－1699(2014)01－0032－08

2013－12－01修改日期:2013－12－28

C:1265H;2570D

10.3969/j.issn.1004－1699.2014.01.007

項目來源:National Natural Science Foundation of China(61036004)